3D NAND Staircase Support Structure for Word Line Stability
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Solution Overview
Problem
Conventional vertical memory array configurations in microelectronic devices, such as 3D NAND Flash memory devices, face issues like word line thickness variations, bending, bowing, and current leaks, which diminish memory device performance, reliability, and durability due to increased feature packing densities and reduced margins for formation errors.
Innovation Solution
The introduction of a microelectronic device structure with a stack of vertically alternating conductive and insulating tiers, featuring a staircase structure with contact and support structures that prevent tier deformation and damage, utilizing specific geometric configurations and material compositions to enhance electrical access and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature packing density is increased to enhance memory density, then memory density is improved, but word line thickness variations, bending, and bowing occur that worsen manufacturing precision and reliability
Solution Approach 1:
The patent divides the continuous word line structure into segmented sections with varying thicknesses along the vertical extent of the stack structure. This segmentation allows different portions of the word line to have optimized thicknesses, preventing uniform thinning that would cause punching through while maintaining electrical connectivity. The segmented approach resolves the contradiction by enabling high memory density through vertical stacking without requiring uniformly thin word lines throughout.
Solution Approach 2:
The patent implements local quality by varying the thickness of word lines at different vertical positions within the stack structure. Specifically, word lines have greater thickness at certain regions (such as at or near the middle vertical extent) compared to other regions. This local variation in thickness provides enhanced mechanical support and electrical conductivity where needed, while maintaining thinner sections where space is constrained, thus preventing deformation and punching through while achieving high memory density.
2Quantity of substance
If feature packing density is increased to enhance memory density, then memory density is improved, but word line bending and bowing occur that worsen structural stability
Solution Approach 1:
The patent segments the word line structure into multiple sections with different thickness characteristics along the vertical direction. This segmentation creates a more robust structural framework that resists bending and bowing forces. By having thicker sections at strategic locations (such as mid-height regions), the overall structural stability is enhanced while still achieving high memory density through the vertical stack architecture.
Solution Approach 2:
The patent applies local quality by providing enhanced thickness and structural reinforcement at specific vertical positions within the word line structure. This localized strengthening prevents bending and bowing in regions most susceptible to deformation, while allowing thinner sections in other areas to maximize packing density. The non-uniform thickness distribution optimizes both structural stability and memory density.
3Quantity of substance
If feature packing density is increased to enhance memory density, then memory density is improved, but current leaks occur that worsen device reliability
Solution Approach 1:
The patent segments the word line structure to create varied thickness profiles that prevent current leakage. By having thicker sections at critical locations, the patent ensures adequate insulation and prevents punching through of underlying structures that would cause current leaks. This segmented thickness variation maintains reliable electrical isolation while achieving high memory density through vertical stacking.
Solution Approach 2:
The patent implements local quality by varying word line thickness at different vertical positions to prevent current leakage. Thicker sections are provided at locations where insulation and electrical isolation are most critical, preventing punching through and current leaks. This localized thickness optimization ensures device reliability while maintaining high memory density through the vertical stack configuration.
Data Source
AI summary
A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.