3D NAND Stairs Contact Layout for Smaller Contact Regions
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Solution Overview
Problem
There is a need to reduce the area of the contact region (stairs region) in three-dimensional NAND nonvolatile memory devices to improve efficiency and reduce the overall size of the semiconductor memory device.
Innovation Solution
The semiconductor memory device incorporates a stacked body with a first and second stairs portion, where a first lower contact passes through the second stairs portion, connected to a conductive layer in the first stairs portion, and a second contact is connected to a conductive layer in the second stairs portion, with the patterns of these stairs portions shifted in the X direction to optimize contact placement and reduce the area of the stairs region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the contact region area is reduced, then the overall device size and area efficiency are improved, but the manufacturing complexity and precision requirements increase
Solution Approach 1:
The patent shifts the contact placement from a conventional planar arrangement to a three-dimensional configuration where contacts are positioned at different vertical levels (first stairs portion and second stairs portion). This dimensional transition allows the contact region to utilize vertical space, thereby reducing the horizontal footprint while maintaining adequate separation and connectivity between contacts.
Solution Approach 2:
The contact region is segmented into multiple discrete contact points positioned at different locations: some contacts are placed at the first stairs portion while others are placed at the second stairs portion. This segmentation allows each contact to be independently positioned and manufactured, reducing the overall area required while maintaining manufacturing feasibility through modular contact placement.
2Area of stationary object
If the stairs region area is reduced, then the device becomes more compact, but the electrical connectivity and contact reliability may be compromised
Solution Approach 1:
By transitioning to a three-dimensional contact arrangement with contacts positioned at different vertical levels (first and second stairs portions), the patent maintains electrical connectivity pathways while reducing the horizontal area. The vertical stacking preserves conductive paths without requiring larger planar contact regions.
Solution Approach 2:
The stairs structure serves multiple functions simultaneously: it provides mechanical support, establishes electrical connectivity pathways, and enables compact area utilization. The same structural elements (stacked conductive layers and insulating layers) fulfill both structural and electrical functions, allowing area reduction without compromising connectivity reliability.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body including a first stacked portion including lower conductive layers stacked in a first direction and including a first stairs portion having a first end portion stepwise processed, and a second stacked portion provided on an upper side of the first stacked portion and including upper conductive layers stacked in the first direction and including a second stairs portion located above the first stairs portion and having a second end portion stepwise processed, and a first lower contact passing through the second stairs portion and connected to a portion of a first lower conductive layer, the portion being included in the first stairs portion.