NAND Memory Status Read via Shared Data I/O Terminals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Issuing status read commands for each individual NAND flash memory chip in a solid-state drive (SSD) is time-consuming, affecting NAND memory performance.
Innovation Solution
A memory system design where ready/busy signals from multiple NAND chips are collectively transferred to the controller using a shared data strobe signal, allowing simultaneous status reading without the need for dedicated output terminals, thereby reducing the time required for status determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If status read commands are issued for each individual NAND flash memory chip, then the controller can determine the processing state of each chip, but the operation time increases and NAND memory performance deteriorates
Solution Approach 1:
The patent merges the status read operations of multiple NAND chips by connecting their ready/busy signals to a common data input/output terminal. Instead of issuing separate status read commands to each chip, the controller can read the status of multiple chips simultaneously through the shared terminal, significantly reducing the time required for status determination while maintaining accurate status detection for each individual chip.
2Ease of operation
If dedicated output terminals are provided for ready/busy signals of each NAND chip, then status reading can be simplified, but the device area increases
Solution Approach 1:
The patent makes the data input/output terminal universal by enabling it to serve multiple functions: it can transfer data between the controller and NAND chips during normal operations, and simultaneously function as a shared terminal for reading ready/busy signals from multiple chips. This multi-functionality eliminates the need for separate dedicated output terminals for each chip's ready/busy signal, reducing the controller's terminal count and overall area while maintaining ease of status reading operations.
Data Source
AI summary
A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.