NAND Storage System Command Overlap for Bus Efficiency

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Solution Overview

Problem

Conventional storage systems using NAND devices face inefficiencies in data transfer due to long busy times, low bus utilization, and difficulties in overlapping commands during initialization, high temperatures, and data burst configurations, leading to suboptimal data transfer efficiency.

Innovation Solution

A storage system with an arithmetic processing device and a storage device that includes a command management unit and a notifying unit to manage and notify the arithmetic processing device about the availability of storing units, allowing for the selection of available units for processing and enabling overlapping of commands without waiting for busy states to end, thereby improving bus efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional read/write processes are used with NAND devices, then data transfer is performed sequentially, but the bus use efficiency is low due to long busy time periods requiring waiting

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidbusy time period
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent enables continuous data transfer by overlapping multiple data transfer operations. While one NAND device is in busy state transferring data, the controller initiates new transfer commands to other NAND devices, eliminating idle waiting time and maintaining continuous bus utilization. This is achieved through a transfer command queue that manages multiple pending transfer operations.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The controller pre-issues transfer commands to NAND devices before previous transfer operations complete. By preparing and queueing transfer commands in advance, the system ensures that the bus is continuously utilized without gaps, as new transfers are initiated while previous transfers are still in progress.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If conventional sequential processing is used, then simple control is maintained, but bus utilization is low because execution must wait during busy periods

Engineering Contradiction:
Improvebus use efficiencyVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a transfer command queue as an intermediary data structure between the host and NAND devices. This queue buffers transfer commands, allowing the controller to manage multiple pending operations systematically. The queue acts as a mediator that decouples the host's command issuance from the actual execution timing, enabling efficient overlapping transfers without complex real-time control logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If data transfer waits for busy state completion, then simple command management is used, but transfer speed is limited by sequential processing

Engineering Contradiction:
Improvedata transfer rateVSAvoidcommand management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements dynamic command management where the controller adaptively issues transfer commands based on the current state of NAND devices. The system dynamically adjusts the timing and sequencing of transfer operations, switching from static sequential processing to dynamic parallel processing. This allows the system to maximize transfer speed by continuously adapting command issuance to available device states.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9977602B2Storage system, storage device, and control method of storage system
Publication Date: 2018.05.22 FUJITSU LTD
  • US9977602B2 patent drawing
  • US9977602B2 patent drawing
  • US9977602B2 patent drawing

AI summary

The storage device includes multiple NAND devices each of which performs a process on the basis of a command; a command management unit that issues the command from a host to one of the NAND devices specified by the command and that sends an issue completion notification of the issued command to the host; and a state notifying unit that notifies, based on whether each of the NAND devices performs a predetermined process, the host whether each of the NAND devices is ready to accept the command. The host includes a NAND control unit that selects one of the NAND devices that is ready to accept the command based on the notification from the state notifying unit when the issue completion notification is received and sends, to the command management unit, a command to allow the selected one of the NAND devices to perform the process.