Shared-Bus NAND Storage Architecture for Throughput-Safe Peer Exchange
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Solution Overview
Problem
Nonvolatile memory devices sharing information with each other can hinder the operation of a storage device, leading to decreased throughput and suboptimal performance that does not satisfy communication standards.
Innovation Solution
A storage device architecture that allows nonvolatile memory devices to communicate information without direct control from the memory controller, using separate signal lines for command and address signals and data strobe signals, enabling synchronized data transfer and inter-device communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If nonvolatile memory devices share information with each other through common signal lines, then information exchange capability is improved, but control of memory devices is hindered and throughput decreases
Solution Approach 1:
The patent segments the signal lines into two distinct groups: first signal lines dedicated for command/address transmission under memory controller management, and second signal lines dedicated for data bit transmission. This segmentation allows memory devices to exchange information through the first signal lines during idle periods without interfering with the controller's ability to manage data transmission through the second signal lines, thereby resolving the contradiction between information exchange capability and throughput.
2Loss of information
If nonvolatile memory devices share information with each other, then information exchange is enabled, but communication standard compliance is not satisfied
Solution Approach 1:
The patent implements dynamic mode switching capability where memory devices can operate in different modes: a first mode enabling information exchange through the first signal lines when no commands are received, and a second mode prioritizing communication standard compliance when commands are being processed. This dynamic adaptation allows the system to satisfy communication standards during controlled operations while enabling information exchange during idle periods.
Solution Approach 2:
The patent changes the operational parameters of the memory devices based on the presence or absence of commands from the memory controller. When commands are present, the system operates in a controlled mode satisfying communication standards; when commands are absent, the system transitions to an information exchange mode. This parameter change approach allows the system to meet communication standard requirements while enabling peer-to-peer information exchange.
3Productivity
If memory devices exchange information during idle periods, then throughput is improved, but operational interference may occur
Solution Approach 1:
The patent extracts the information exchange function from the data transmission path by dedicating the first signal lines for this purpose. Memory devices can exchange information through the first signal lines during idle periods without affecting the second signal lines used for data transmission under controller management. This extraction eliminates operational interference between information exchange and controlled data transmission operations.
Data Source
AI summary
There is provided a storage device which includes a plurality of nonvolatile memory devices, and a memory controller connected in common to the plurality of nonvolatile memory devices through first signal lines and connected in common to the plurality of nonvolatile memory devices through second signal lines. Each of the plurality of nonvolatile memory devices receives a command and an address through the first signal lines and communicates data bits with the memory controller through the second signal lines. While the command and the address are not received through the first signal lines, the plurality of nonvolatile memory devices exchange information through the first signal lines without control of the memory controller.