NAND String Block Interleaving for Higher Write Throughput
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Solution Overview
Problem
Existing memory systems face inefficiencies due to unorganized programming of NAND flash memory blocks with varying programming characteristics, leading to slower data transfer rates and reduced system throughput.
Innovation Solution
Implementing an interleaved programming method for erase blocks coupled to the same string, allowing separate access and operation of blocks with different programming characteristics to improve average write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential programming of erase blocks is used, then programming simplicity is maintained, but write throughput is reduced due to consecutive access to slower blocks
Solution Approach 1:
The patent applies dynamics by making the programming sequence flexible and adaptive rather than fixed. The system dynamically selects which erase blocks to program next based on their programming speeds, transitioning from a static sequential approach to a dynamic interleaved approach that optimizes throughput in real-time
Solution Approach 2:
The patent implements periodic action through interleaved programming where the system alternates between programming different erase blocks in a periodic pattern. This periodic switching between blocks with different programming characteristics ensures that the system doesn't get stuck on slow blocks, maintaining higher average throughput
2Productivity
If interleaved programming of erase blocks is implemented, then write throughput is improved, but control complexity increases
Solution Approach 1:
The patent applies feedback by continuously monitoring the programming speeds of different erase blocks and using this information to adjust the programming sequence. The system measures actual programming performance and feeds this back into the scheduling algorithm to optimize the interleaved pattern, making the control adaptive rather than purely predetermined
Solution Approach 2:
The patent changes the parameter of block access pattern from sequential to interleaved, and further optimizes by adjusting the interleaving pattern based on measured programming characteristics. This parameter change allows the system to transform the access sequence to match the actual performance characteristics of different blocks
Data Source
AI summary
A method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. The method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.