3D NAND Memory String Layout for Narrow-Trench Contact Conductivity
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Solution Overview
Problem
Existing memory array technologies face challenges in efficiently forming memory cells with optimal contact areas and conductivity, particularly in narrower trenches and thinner conductive tiers, which can affect the performance and efficiency of memory arrays.
Innovation Solution
The method involves forming memory arrays with vertically alternating conductive and insulative tiers, creating channel-material-string constructions that include charge-blocking, storage, and charge-passage materials, and using conductive material to directly couple channel material with the conductor tier, optimizing the contact area and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If narrower trenches and thinner conductive tiers are used in memory array formation, then device density and integration are improved, but contact area and conductivity deteriorate
Solution Approach 1:
The patent implements a nested structure where conductive material is placed within the trench to form a conductive tier that is surrounded by insulative material. This nested arrangement allows the conductive tier to be embedded within the insulative material, maximizing contact area while maintaining compact dimensions for high device density.
Solution Approach 2:
The patent transitions from planar contact interfaces to three-dimensional contact structures by forming conductive tiers that extend vertically within trenches. This dimensional change increases the contact area between conductive and semiconductive materials without increasing the lateral footprint, thereby maintaining high device density while improving conductivity.
2Ease of manufacture
If conventional forming methods are used for memory cells, then manufacturing process simplicity is maintained, but contact area and conductivity are insufficient
Solution Approach 1:
The patent segments the memory array formation into distinct sequential steps: forming insulative tiers with trenches, depositing conductive material to form conductive tiers, and forming semiconductive material. This segmentation allows each layer to be optimized independently while maintaining overall process simplicity through standard semiconductor fabrication techniques.
Solution Approach 2:
The patent performs preliminary actions by first forming the insulative tiers and trenches before depositing the conductive material. This preliminary structuring establishes the framework for subsequent conductive tier formation, ensuring proper contact area and conductivity are achieved before final semiconductive material deposition.
Data Source
AI summary
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conductive material is laterally-aside and laterally-inward of a laterally-inner sidewall of the charge-blocking-material string. Methods are disclosed.