NAND String p-Well Biasing for Faster Read Stabilization
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Solution Overview
Problem
Existing memory devices face challenges in achieving accurate read operations with short read times, as stabilizing word lines and bit lines during reading can lead to increased fail bit counts due to insufficient time for stabilization, exacerbated by high RC delay.
Innovation Solution
Implementing a control mechanism that adjusts the source voltage signal (Vcelsrc) and body voltage signal (Vp-well) of a NAND string during read operations, including a negative voltage kick to reduce channel resistance, by temporarily reducing Vcelsrc and maintaining Vp-well constant or increasing it, to enhance current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If word lines and bit lines are stabilized during read operations, then read accuracy is improved, but read time increases due to high RC delay
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a specific voltage level before read operations and pre-establishing word line voltages. This preparation ensures that when the actual read operation occurs, the lines are already in an optimal state for rapid signal detection, thereby reducing the stabilization time required during the read operation itself while maintaining high read accuracy.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting voltage levels on word lines and bit lines during different phases of the read operation. By changing voltage parameters optimally for each phase (pre-charge, read, verify), the system achieves fast stabilization without sacrificing measurement precision, effectively resolving the contradiction between speed and accuracy.
2Productivity
If read operation time is reduced, then productivity is improved, but fail bit counts increase due to insufficient stabilization time
Solution Approach 1:
The patent implements periodic action through a structured sequence of voltage pulses and timing cycles during read operations. The method employs periodic pre-charging, reading, and verifying phases with optimally timed intervals. This periodic structure ensures that each phase has sufficient time to complete its function reliably while the overall cycle time remains minimized, thus improving productivity without increasing fail bit counts.
Solution Approach 2:
By performing preliminary pre-charging of bit lines and pre-establishment of word line voltages before the actual read operation, the patent ensures that the critical read phase can complete quickly without compromising reliability. The preliminary actions prepare the system in advance, allowing the main read operation to proceed at high speed with minimal risk of read failures.
3Power
If channel resistance is reduced during read operations, then current flow is improved, but voltage stability becomes difficult to maintain
Solution Approach 1:
The patent applies dynamics by making the voltage configuration adaptive and time-dependent. Different voltage levels are applied to word lines and bit lines at different times during the read operation sequence. The system dynamically transitions between voltage states (pre-charge voltage, read voltage, verify voltage) to optimize current flow when needed while maintaining stability during critical measurement phases, thus resolving the contradiction between power and stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the channel resistance and current flow, reducing read time while minimizing fail bit counts and improving read accuracy.
Implementation Method 1
a body voltage signal, Vp-well, of a substrate of the NAND string are controlled to reduce the channel resistance
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.