NAND Memory String Programming With Aligned Verification Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The writing speed in NAND memory is slowed due to the need for verification reading processes.
Innovation Solution
The semiconductor storage device employs a sense amplifier module that controls the direction of current flow during writing and reading operations to align with the direction of data verification, using Normal Order Program (NOP) and Reverse Order Program (ROP) modes, and Sub-Block Mode (SBM) to optimize writing speed by reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification reading is performed during data writing to memory cells, then data accuracy is ensured, but writing speed becomes slow
Solution Approach 1:
The patent applies preliminary action by performing verification reading in the same direction as data writing (Normal Order Program mode). The sense amplifier reads data from memory cells in the same sequence that data is being written, allowing verification to occur concurrently with the writing process rather than requiring separate verification steps, thus maintaining data accuracy while improving writing speed
Solution Approach 2:
The patent employs inversion by introducing Reverse Order Program (ROP) mode where the direction of data writing is reversed relative to the verification reading direction. By alternating between NOP and ROP modes for different memory blocks, the system optimizes the alignment between writing and reading directions, reducing parasitic resistance and enabling faster verification that doesn't bottleneck the overall writing speed
2Reliability
If current flow direction during reading is not aligned with writing direction, then verification can be performed, but parasitic resistance increases and writing speed decreases
Solution Approach 1:
The patent applies dynamics by making the current flow direction adjustable and adaptive. The control circuit dynamically selects between Normal Order Program (NOP) mode where reading and writing directions align, and Reverse Order Program (ROP) mode where they are reversed. This dynamic switching allows the system to optimize current flow direction based on which memory block is being written, minimizing parasitic resistance and maximizing writing speed while maintaining verification capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances writing speed by aligning current flow directions during writing and reading, thereby reducing resistance and improving overall data transfer efficiency in NAND memory.
Implementation Method 1
enhances writing speed by aligning current flow directions during writing and reading, thereby reducing resistance
Data Source
AI summary
In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.