3D NAND Memory Strings With Etch-Stop Channel Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory array fabrication methods face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architecture, which affects the performance and reliability of non-volatile memory devices.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays, utilizing vertically-alternating tiers of conductive and insulative materials, with non-stoichiometric silicon dioxide as an etch stop, allowing precise formation of channel openings and trenches for memory cell structures, followed by deposition of transistor materials and conductive lines to create reliable memory cell strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are formed using conventional fabrication methods, then memory array capacity is increased, but structural integrity and electrical connectivity reliability deteriorate
Solution Approach 1:
The patent applies preliminary action by forming sacrificial structures (first and second sacrificial structures) before finalizing the memory cell stack. These sacrificial structures are used to define precise openings and pathways that guide subsequent material deposition and etching processes, ensuring proper alignment and structural integrity of the vertically-stacked memory cells before they are fully formed.
Solution Approach 2:
The patent uses intermediary materials and structures including dielectric layers, conductive layers, and sacrificial structures as mediators during fabrication. These intermediary elements facilitate the formation of reliable electrical connections between stacked memory cells by providing temporary support structures and precise patterning guides that are later removed or integrated into the final device architecture.
2Manufacturing precision
If gate-last or replacement-gate processing is used to form memory arrays, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The gate-last or replacement-gate processing uses preliminary action by first forming all other memory cell structures (channel openings, trenches, conductive layers) before finally forming or replacing the gate structures. This sequencing allows precise definition of opening geometries using sacrificial structures as templates, achieving high manufacturing precision while managing process complexity through systematic fabrication steps.
Solution Approach 2:
The replacement-gate approach extracts or removes the traditional gate formation step from the conventional sequence, instead forming gates after other structures are in place. This extraction allows for more precise control of channel opening geometries and enables better integration of vertically-stacked components, improving manufacturing precision at the cost of increased process complexity.
3Manufacturing precision
If non-stoichiometric silicon dioxide is used as etch stop, then manufacturing precision is improved, but material complexity increases
Solution Approach 1:
The patent applies parameter changes by utilizing non-stoichiometric silicon dioxide with specific oxygen deficiency characteristics as an etch stop layer. The controlled deviation from stoichiometric composition (SiO2) provides distinct etching selectivity that enables precise termination of etching processes at desired interfaces, improving manufacturing precision. While this introduces material complexity, the benefit of precise opening formation justifies the use of this specialized material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the structural integrity and electrical connectivity of memory cells, improving the performance and reliability of non-volatile memory arrays by ensuring precise formation and integration of memory cell structures within the array.
Implementation Method 1
utilizing vertically-alternating tiers of conductive and insulative materials, with non-stoichiometric silicon dioxide as an etch stop
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.