NAND Data Striping Across Pages and Planes for Error Recovery
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Solution Overview
Problem
Traditional NAND memory devices are vulnerable to data loss due to programming failures and asynchronous power losses, which can corrupt entire pages or planes, leading to unrecoverable data errors.
Innovation Solution
An improved NAND data placement schema is implemented, where data is striped across different page lines and planes, with parity information calculated and stored to ensure that data loss is limited to a single portion, allowing for recovery using XOR operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in traditional NAND memory pages, then storage capacity is maximized, but vulnerability to programming failures and power losses increases
Solution Approach 1:
The patent divides data items into multiple portions and stores them across different pages and planes in the NAND memory array. This segmentation ensures that a programming failure or power loss affecting one page does not corrupt the entire data item, as other portions stored in different locations remain intact and can be used for recovery.
Solution Approach 2:
The patent implements differential storage strategies where different portions of data items are stored with different levels of redundancy based on their importance and error probability. Parity information is strategically placed in specific locations (such as SLC-coupled pages) to provide localized protection against failures in specific regions of the memory array.
2Reliability
If parity information is stored to enable error recovery, then data reliability improves, but storage capacity for user data decreases
Solution Approach 1:
The patent merges parity storage with existing memory structures by utilizing spare pages and planes that are already part of the NAND memory architecture. Instead of adding separate dedicated parity storage regions, the solution integrates error correction capabilities into the existing page and plane structure, thereby minimizing the impact on user data capacity.
Solution Approach 2:
The patent creates redundant copies of critical data portions and parity information in strategically selected locations within the memory array. These copies are placed in pages with lower error probabilities or in planes that are less susceptible to programming failures, providing backup capacity without requiring complete duplication of the entire storage system.
3Reliability
If data is striped across multiple pages and planes, then error recovery capability improves, but data placement complexity increases
Solution Approach 1:
The patent pre-establishes a systematic data placement schema that defines specific rules for distributing data portions and parity information across pages and planes before actual data storage occurs. This preliminary organization includes predetermined mappings between data items and their constituent portions, as well as predefined locations for parity information, which simplifies the storage operation and enables efficient recovery procedures.
Solution Approach 2:
The patent implements monitoring mechanisms that track the storage status and error characteristics of different pages and planes. This feedback information is used to dynamically adjust data placement decisions, directing new data portions to locations with demonstrated reliability and identifying pages that may require additional parity protection or should be avoided for critical data storage.
Data Source
AI summary
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.