3D NAND Memory Strobe Tier Scan for Peak Current Reduction
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Solution Overview
Problem
Non-volatile memory devices face challenges in reducing current consumption, particularly in portable electronic devices, where peak current requirements must be met, and existing technologies struggle to efficiently manage the programming of multi-level cells in 3D NAND structures.
Innovation Solution
A memory apparatus and method that includes memory cells arranged in tiers, with a control means or controller configured to select a predetermined strobe quantity of tiers for single-level and multi-level cells, allowing for separate operation and sensing during verify operations, thereby optimizing current consumption and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells are programmed in 3D NAND structures, then storage capacity is increased, but peak current consumption increases
Solution Approach 1:
The memory device segments the tiers into different groups (first group for SLC, second group for MLC/TLC) and applies different strobe quantities to each group during verify operations. This segmentation allows the device to reduce the strobe quantity for MLC/TLC tiers compared to SLC tiers, thereby reducing peak current consumption while maintaining storage capacity
Solution Approach 2:
The control means dynamically adjusts the strobe quantity based on the cell type (SLC vs. MLC/TLC) and operation mode. The strobe quantity is changed from a fixed value to a variable parameter that adapts to different verification requirements, enabling current consumption optimization without sacrificing programming efficiency
2Reliability
If verify operations are performed on all tiers, then programming accuracy is maintained, but current consumption increases
Solution Approach 1:
Different verify operation qualities are applied to different tier groups. SLC tiers receive full-precision verification with higher strobe quantities, while MLC/TLC tiers receive optimized verification with reduced strobe quantities. This local differentiation maintains programming accuracy where critical while reducing current consumption where possible
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.