Variable-Size NAND Sub-Blocks for Erase and Mapping Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As non-volatile memory devices increase in capacity and miniaturization, dividing memory blocks into sub-blocks of varying sizes complicates erase operations and management, leading to increased resource requirements and performance deterioration.

Innovation Solution

A non-volatile memory device with sub-blocks of different sizes, each connected to distinct word line groups, utilizes a storage controller to manage separate mapping tables and perform efficient erase operations by considering the physical and electrical characteristics of each sub-block, optimizing data density and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If memory blocks are divided into sub-blocks of varying sizes to meet capacity and miniaturization demands, then storage capacity and device size are improved, but erase operation complexity and resource requirements increase

Engineering Contradiction:
Improvestorage capacityVSAvoiderase operation complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The memory block is divided into multiple sub-blocks with different sizes based on the number of word lines. Each sub-block is independently erasable, allowing flexible management of varying capacity requirements while maintaining manageable erase operation units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different sub-blocks are assigned different sizes according to their specific word line counts and operational characteristics. This local differentiation allows each sub-block to be optimized for its specific function while the overall system maintains unified management through the controller.

Inventive Principle:
Principle #3Local quality

2Volume of moving object

If sub-blocks of different sizes are used to increase capacity, then storage capacity is improved, but management complexity and firmware requirements increase

Engineering Contradiction:
Improvestorage capacityVSAvoidmanagement complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The storage controller is designed to universally manage all sub-blocks regardless of their size differences. It maintains a unified interface for garbage collection and wear leveling operations, making the management system multi-functional and adaptable to varying sub-block configurations without requiring separate management mechanisms for each sub-block size.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Volume of moving object

If sub-blocks of different sizes are implemented, then storage capacity is improved, but performance deteriorates due to increased resource requirements

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice performance
Core Design Contradiction:
Volume of moving objectVSProductivity

Solution Approach 1:

The storage controller dynamically adjusts its management strategies based on the specific characteristics of each sub-block. It can selectively perform operations on different sub-blocks based on their sizes and current operational needs, optimizing resource allocation and maintaining high performance despite the presence of varying sub-block configurations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12512157B2Non-volatile memory device including sub-blocks having different sizes and storage device
Publication Date: 2025.12.30 SAMSUNG ELECTRONICS CO LTD
  • US12512157B2 patent drawing
  • US12512157B2 patent drawing
  • US12512157B2 patent drawing

AI summary

A non-volatile memory device is provided. The non-volatile memory device includes: sub-blocks provided on a substrate. The sub-blocks include: a first sub-block connected to a first word line group including a first number of word lines; and a second sub-block connected to a second word line group including a second number of word lines. The first sub-block includes: at least one first memory cell storing M-bit data; and second memory cells each storing N-bit data. The second sub-block includes: at least one third memory cell storing K-bit data; and fourth memory cells each storing L-bit data. M, N, K, and L are positive integers, N is greater than M, and L is greater than K. The first number and the second number are different, and the at least one first memory cell and the at least one third memory cell include different numbers of memory cells.