NAND Flash Sub-Block Erase Control for Storage Mode Wear Reduction
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Solution Overview
Problem
Existing memory systems face inefficiencies in data storage and management, particularly in nonvolatile memory devices like NAND flash, due to the lack of effective strategies for managing storage modes and reducing wear on memory cells, leading to reduced performance and lifespan.
Innovation Solution
A memory system with a memory controller that independently executes data erase operations for each physical sub-block within a physical full block, ensuring all sub-blocks within a logical sub-block operate in the same storage mode, thereby reducing the need for frequent mode changes and enhancing data management efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data erase operations are executed independently for each physical sub-block, then memory cell wear is reduced and lifetime is extended, but device complexity increases due to independent management of multiple sub-blocks
Solution Approach 1:
The memory device is divided into multiple physical full blocks, each containing multiple physical sub-blocks. The controller independently manages erase operations for each sub-block rather than treating the entire block as a single unit. This segmentation allows selective erasure of only the necessary sub-blocks, reducing unnecessary wear on memory cells that are still in use and extending the overall memory system lifetime.
Solution Approach 2:
The system dynamically adjusts the storage mode (e.g., SLC, MLC, TLC) for different physical sub-blocks based on their individual usage patterns and wear levels. This dynamic management allows the controller to optimize performance and durability for each sub-block independently, while implementing a unification strategy that groups sub-blocks with the same storage mode to simplify control operations.
2Device complexity
If all physical sub-blocks within a physical full block are set to the same storage mode, then control complexity is reduced, but adaptability to different data management requirements is limited
Solution Approach 1:
The memory device is divided into multiple physical full blocks, each containing multiple physical sub-blocks. The controller independently manages erase operations for each sub-block rather than treating the entire block as a single unit. This segmentation allows selective erasure of only the necessary sub-blocks, reducing unnecessary wear on memory cells that are still in use and extending the overall memory system lifetime.
Solution Approach 2:
The system dynamically adjusts the storage mode (e.g., SLC, MLC, TLC) for different physical sub-blocks based on their individual usage patterns and wear levels. This dynamic management allows the controller to optimize performance and durability for each sub-block independently, while implementing a unification strategy that groups sub-blocks with the same storage mode to simplify control operations.
Data Source
AI summary
A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of physical full blocks. Each of the plurality of physical full blocks includes a plurality of physical sub-blocks. The memory controller executes a data erase operation independently for each of the plurality of physical sub-blocks in each of the plurality of physical full blocks, and in each of the plurality of physical full blocks, sets all of the plurality of physical sub-blocks therein to a same storage mode. The storage mode set for a physical sub-block indicates the number of bits of data stored in a memory cell thereof.