NAND Memory Sub-Block Mapping for Erase Management

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Solution Overview

Problem

As the number of word lines increases on a substrate to meet demands for high capacity and miniaturization in non-volatile memory devices, the varying sizes of memory blocks lead to increased resource requirements and complexity in erase operations, management, and firmware for garbage collection, deteriorating storage device performance.

Innovation Solution

A non-volatile memory device with sub-blocks of different sizes is managed by a storage controller that determines data densities and reliabilities of memory cells, performing address mapping to optimize erase operations and reduce resource requirements through independent management of sub-blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of word lines is increased to meet high capacity and miniaturization demands, then storage capacity and device density are improved, but the size of memory blocks increases leading to higher resource requirements and complexity in erase operations and management

Engineering Contradiction:
Improvestorage capacityVSAvoidcomplexity of management and firmware
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory block is divided into multiple sub-blocks that can be independently managed and erased. This segmentation allows the controller to perform erase operations on smaller units, reducing the resource requirements and complexity associated with managing large blocks while maintaining high storage capacity through the increased number of word lines.

Inventive Principle:
Principle #1Segmentation

2Productivity

If memory blocks are divided into sub-blocks to manage erase operations, then erase operation efficiency is improved, but resource requirements and management complexity increase when sub-blocks have different sizes

Engineering Contradiction:
Improveerase operation efficiencyVSAvoidcomplexity of management and firmware
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Different sub-blocks are assigned different sizes based on local requirements and characteristics. The controller manages these varied sub-blocks by determining appropriate data densities and reliabilities for each, allowing optimized erase operations while handling the complexity through targeted management strategies for each sub-block region.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If sub-blocks of different sizes are used to optimize storage, then storage capacity utilization is improved, but resource requirements for erase operations and management increase

Engineering Contradiction:
Improvestorage capacity utilizationVSAvoidresource requirements for erase operations
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The controller dynamically determines data densities and reliabilities for different sub-blocks based on their specific characteristics and usage patterns. This dynamic adaptation allows the system to optimize storage capacity utilization while managing resource requirements for erase operations by adjusting parameters according to actual sub-block conditions rather than using fixed approaches.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4372749B1Non-volatile memory device and storage device
Publication Date: 2026.03.18 SAMSUNG ELECTRONICS CO LTD
  • EP4372749B1 patent drawingFigure 1
  • EP4372749B1 patent drawingFigure 2
  • EP4372749B1 patent drawingFigure 3

AI summary

A non-volatile memory device is provided. The non-volatile memory device includes: sub-blocks provided on a substrate. The sub-blocks include: a first sub-block connected to a first word line group including a first number of word lines; and a second sub-block connected to a second word line group including a second number of word lines. The first sub-block includes: at least one first memory cell storing M-bit data; and second memory cells each storing N-bit data. The second sub-block includes: at least one third memory cell storing K-bit data; and fourth memory cells each storing L-bit data. M, N, K, and L are positive integers, N is greater than M, and L is greater than K. The first number and the second number are different, and the at least one first memory cell and the at least one third memory cell include different numbers of memory cells.