NAND Memory Sub-Block Parallel Programming for Lower Latency

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Solution Overview

Problem

The iterative process of programming and verifying cells in NAND flash memory is time-consuming, leading to performance concerns.

Innovation Solution

Simultaneously programming multiple sub-blocks in NAND memory structures by boosting all sub-blocks, applying data to bitlines, and using a single program pulse to program cells in multiple sub-blocks simultaneously.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If iterative programming and verifying process is used for NAND flash memory, then programming accuracy is ensured, but programming time increases significantly

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogramming time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The memory array is divided into multiple independent sub-blocks that can be programmed simultaneously. Each sub-block contains its own set of memory cells, bitlines, and control circuitry, allowing parallel programming operations without interfering with each other. This segmentation enables multiple programming operations to occur concurrently, reducing total programming time while maintaining verification accuracy for each sub-block

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple sub-blocks are merged into a single programming operation by applying program pulses to wordlines that span across all sub-blocks simultaneously. The control circuitry coordinates the programming of multiple sub-blocks in parallel, combining what would traditionally be sequential operations into a single time window, thereby reducing overall programming latency

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If multiple sub-blocks are programmed simultaneously, then programming speed increases, but control complexity increases

Engineering Contradiction:

Improveprogramming speedVSAvoidcontrol complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The control circuitry is designed with multi-functionality to handle both single-sub-block and multi-sub-block programming operations. The same control logic can dynamically configure the memory array to program one or multiple sub-blocks simultaneously by adjusting wordline and bitline voltage assignments, providing flexibility without requiring separate dedicated control paths for each mode

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control circuitry pre-configures the voltage levels and signal assignments for all sub-blocks before initiating the programming operation. By preparing the control signals in advance and establishing the parallel programming architecture beforehand, the system reduces the complexity of coordinating multiple simultaneous operations during the actual programming process

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250308591A1Simultaneous Programming Of Multiple Sub-Blocks In Nand Memory Structures

Publication Date: 2025.10.02 INTEL NDTM US LLC

AI summary

Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.