NAND Sub-Block Pre-Charge Timing to Prevent Program Disturb

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Solution Overview

Problem

Existing non-volatile memory technologies face challenges in reliably preventing disturb of unselected memory cells during programming, particularly when certain portions lack access to pre-charging sources, leading to unsuccessful boosting and potential data loss.

Innovation Solution

Implementing a pre-charge operation for memory cells in vertically stacked sub-blocks, followed by programming pulses and verification pulses in a program loop, with the pre-charge occurring during the verify phase of a previous loop to prevent disturb and ensure reliable programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-charge operation is performed for vertically stacked sub-blocks, then reliability of data storage is improved, but device complexity increases

Engineering Contradiction:

Improvedata storage reliabilityVSAvoidpre-charge operation complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing pre-charge operation for the second sub-block during the verify phase of a previously occurring program loop. This advance preparation ensures that channels are properly charged before the actual programming operation, preventing disturb in unselected memory cells and ensuring reliable data storage without requiring separate pre-charge steps after programming.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the memory block into first and second sub-blocks with different pre-charge timing strategies. The first sub-block receives pre-charge during its own program phase, while the second sub-block receives pre-charge during the verify phase of a previous program loop. This segmentation allows independent optimization of pre-charge operations for each sub-block, improving overall reliability while managing complexity through structured division.

Inventive Principle:

Principle #1Segmentation

2Reliability

If pre-charge operation is performed during verify phase of previous loop, then disturb in unselected memory cells is prevented, but programming time increases

Engineering Contradiction:

Improveprogramming success rateVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the pre-charge operation with the verify phase of a previous program loop. By combining these two operations into a single time period, the system prevents disturb in unselected memory cells without requiring an additional separate pre-charge step. The verify phase naturally occurs before the next program phase, so integrating pre-charge into this window ensures reliability while minimizing time overhead.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent maintains continuity of useful action by performing pre-charge during the verify phase of a previous program loop, which is a period when the memory system is already in an active state. This approach ensures that pre-charge is completed before the next programming operation begins, eliminating idle time and ensuring continuous productive operation of the memory system.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If channels are pre-charged before programming, then successful programming is ensured, but energy consumption increases

Engineering Contradiction:

Improveprogramming success rateVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs pre-charge operation as a preliminary action during the verify phase of a previous program loop, before the actual programming operation for the second sub-block begins. This timing ensures that channels are ready for successful programming while utilizing a period when the system is already in an active state, avoiding the need for additional energy-intensive pre-charge steps after programming is complete.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent leverages the existing verify phase operation to serve the dual purpose of verification and pre-charge preparation. By using the verify phase's electrical state and timing, the system enables pre-charge functionality without requiring a completely separate energy-intensive operation. The verify phase's inherent electrical characteristics are utilized to support the pre-charge requirement, reducing overall energy consumption.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20260044443A1Pre-charge at read recovery clock from bit line side for sub-block one performance improvement

Publication Date: 2026.02.12 SANDISK TECHNOLOGIES LLC

AI summary

A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.