3D NAND Flash Memory Sub-Block Erase Voltage Compensation
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Solution Overview
Problem
Current memory systems face challenges in maintaining data reliability due to variations in threshold voltages after partial erase operations in 3D NAND flash memory devices, leading to read errors and reduced reliability.
Innovation Solution
The method involves dividing memory blocks into sub-blocks and using different program and read methods based on threshold voltage distributions, with the second program method applying a higher voltage and the second read method performing multiple read operations to compensate for voltage shifts and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single program method is used for all memory blocks, then the control logic is simple, but data reliability deteriorates due to threshold voltage variations after partial erase operations
Solution Approach 1:
The memory block is divided into a first sub-block and a second sub-block, allowing different program methods to be applied to different sub-blocks based on their threshold voltage distribution states. This segmentation enables selective application of the first program method (with higher program voltages) to sub-blocks requiring it, while using the second program method (with lower program voltages) on sub-blocks that do not require it, thereby improving data reliability without unnecessarily increasing control logic complexity across the entire memory block.
Solution Approach 2:
Different program methods are applied to different sub-blocks based on their local threshold voltage distribution characteristics. The first sub-block may require the first program method with higher voltages to compensate for threshold voltage shifts, while the second sub-block may suffice with the second program method using lower voltages. This local quality approach ensures that each sub-block receives the appropriate programming treatment for its specific condition, improving overall data reliability while minimizing unnecessary complexity.
2Reliability
If higher program voltages are applied to compensate for threshold voltage shifts, then data reliability improves, but energy consumption increases
Solution Approach 1:
The first program method using higher program voltages is applied only to the first sub-block that exhibits threshold voltage shifts requiring compensation, while the second program method using lower program voltages is applied to the second sub-block that does not require such compensation. This localized application of higher voltages ensures data reliability is improved where needed while minimizing energy consumption by avoiding unnecessary high-voltage programming in sub-blocks that do not require it.
Solution Approach 2:
The program voltage parameter is dynamically adjusted based on the threshold voltage distribution state of each sub-block. When threshold voltage shifts are detected in a sub-block, the program voltage is increased to compensate; when shifts are not detected, the program voltage remains at lower levels. This parameter change strategy maintains data reliability through voltage adjustment only where necessary, thereby reducing overall energy consumption compared to applying high voltages uniformly across all sub-blocks.
3Reliability
If multiple read operations are performed to compensate for voltage shifts, then data reliability improves, but operation time increases
Solution Approach 1:
The memory block is segmented into first and second sub-blocks, allowing the controller to selectively apply multiple read operations only to the first sub-block that exhibits threshold voltage shifts, while using a single read operation for the second sub-block that does not exhibit shifts. This segmentation approach improves data reliability for affected sub-blocks through multiple reads while minimizing time loss by avoiding redundant read operations in unaffected sub-blocks.
Data Source
AI summary
A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.