3D NAND Sub-Plane Source Lines to Reduce Data Disturbs
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Solution Overview
Problem
Existing NAND memory technologies face challenges with data disturbs and high power consumption due to the shared source line across all blocks of a plane, which affects data retention and increases current requirements.
Innovation Solution
The introduction of sub-planes by separating the source line into multiple regions using isolation trenches, allowing each sub-plane to be independently biased, reduces data disturbs and lowers current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared source line is used across all blocks of a plane, then device complexity is reduced, but data disturbs increase and power consumption rises
Solution Approach 1:
The patent divides the plane into multiple sub-planes, with each sub-plane having its own dedicated source line. This segmentation allows independent biasing of source lines for different sub-planes, preventing data disturbs in unselected sub-planes while maintaining manageable device complexity through organized modular structure.
2Device complexity
If a shared source line is used across all blocks of a plane, then device complexity is reduced, but power consumption increases
Solution Approach 1:
By segmenting the plane into sub-planes with dedicated source lines, the patent enables selective activation of only those source lines required for current operations. This reduces overall power consumption compared to a shared source line that must be activated for all blocks, while maintaining acceptable device complexity through systematic organization.
3Productivity
If denser physical structures are used to increase data capacity and speed, then data capacity and operation speed improve, but current requirements and data disturbs increase
Solution Approach 1:
The patent implements segmentation into sub-planes with dedicated source lines, which allows high-density memory structures to operate with reduced data disturbs. By isolating source line biasing to specific sub-planes, the system can maintain high data capacity and operation speed while preventing adverse effects on other memory blocks.
Data Source
AI summary
To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.