3D NAND Support Structure for Gate Stack Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining electrical characteristics and reducing manufacturing costs.
Innovation Solution
The semiconductor device incorporates a gate stack structure with insulating and conductive patterns alternately stacked, a memory channel structure extending through the gate stack, and a support structure that includes an outer support layer contacting the side walls of insulating and conductive patterns, and an inner support layer and support pattern contacting the inner side wall of the outer support layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a support structure is formed to extend through the gate stack structure, then structural support and alignment are improved, but device complexity increases due to multiple layers (outer support layer, inner support layer, support pattern)
Solution Approach 1:
The support structure is segmented into three distinct components: an outer support layer contacting side walls of insulating and conductive patterns, an inner support layer contacting the inner side wall of the outer support layer, and a support pattern at the bottom. This segmentation allows each layer to fulfill specific functional requirements while maintaining overall structural integrity and simplifying the formation process through sequential deposition.
2Quantity of substance
If data storage capacity is increased by implementing three-dimensionally arranged memory cells, then storage density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking. Memory cells are arranged vertically through the gate stack structure, enabling increased storage capacity by utilizing the vertical dimension. The support structure extends through this three-dimensional arrangement to provide structural integrity and maintain precise alignment of stacked components.
3Reliability
If the gate stack structure includes insulating and conductive patterns alternately stacked, then electrical characteristics are enhanced, but device complexity increases
Solution Approach 1:
The gate stack structure employs composite material layers including insulating patterns and conductive patterns alternately stacked. This composite structure combines materials with different electrical properties to achieve enhanced electrical characteristics while maintaining a systematic formation process. The support structure is also formed using composite materials including the outer support layer, inner support layer, and support pattern.
Data Source
AI summary
A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.