3D NAND Support Structure Layout for Capacity and Stability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in the design of memory cell structures and dummy structures within the device.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions, featuring gate electrodes with a stepped shape, interlayer insulating layers, channel structures, and varying dummy and support structures, where the size and shape of the dummy structures differ from the support structures, enhancing structural stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but structural stability and reliability deteriorate
Solution Approach 1:
The memory device is divided into distinct functional regions: a first region containing active memory cells with channel structures, a second region with dummy structures for stress compensation, and a third region with support structures for mechanical stability. This segmentation allows each region to be optimized for its specific function while contributing to overall device reliability.
Solution Approach 2:
Different structural configurations are applied to different regions of the substrate. The first region uses channel structures with semiconductor material for active memory storage, the second region uses dummy structures with larger size for stress compensation, and the third region uses support structures for mechanical reinforcement. This local differentiation optimizes both storage capacity and structural stability.
2Quantity of substance
If gate electrodes are stacked vertically to increase storage capacity, then data storage capacity is improved, but manufacturing precision and structural uniformity worsen
Solution Approach 1:
The gate electrode structure transitions from a uniform two-dimensional arrangement in the first region to a stepped three-dimensional arrangement in the third region, with the second region providing an intermediate transition zone. This gradual local differentiation allows vertical stacking for increased capacity while maintaining manufacturing feasibility and structural uniformity through controlled regional variation.
Solution Approach 2:
The gate electrodes are arranged in a stepped configuration that utilizes the vertical dimension progressively. The first region maintains a lower elevation, the second region provides a transition, and the third region achieves higher vertical stacking. This dimensional transition enables increased storage capacity while accommodating manufacturing constraints through gradual structural evolution.
3Reliability
If dummy structures with larger size are used, then structural stability is improved, but device complexity increases
Solution Approach 1:
The device is segmented into regions with different structural characteristics. The dummy structures in the second region are deliberately designed with larger size than the support structures in the third region, creating a clear functional distinction. This segmentation simplifies the design rationale: larger dummy structures provide stress compensation, while smaller support structures provide mechanical stability, making the overall complexity manageable through functional organization.
Data Source
AI summary
A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.