3D NAND Ground Select Threshold Layout for Interference Control
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Solution Overview
Problem
The increase in integration density of memory devices leads to interference among word lines, string select lines, and ground select lines, degrading the reliability of data storage.
Innovation Solution
A memory device with a memory cell array comprising cell blocks, where ground select transistors in different cell blocks are programmed to distinct threshold voltages, and a control circuitry controls operations to maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density of memory devices is increased, then storage capacity is improved, but interference among word lines, string select lines, and ground select lines increases causing data reliability to deteriorate
Solution Approach 1:
The memory device divides ground select transistors into two distinct groups based on their connection to ground select lines: first ground select transistors connected to GSLs and second ground select transistors not connected to GSLs. This segmentation allows different threshold voltage programming strategies to be applied to each group, reducing interference effects while maintaining high integration density.
Solution Approach 2:
Different threshold voltages are programmed in different locations within the memory structure. Specifically, first ground select transistors are programmed to a first threshold voltage while second ground select transistors are programmed to a second threshold voltage that is higher than the first. This local differentiation in electrical properties allows selective control of interference effects in different regions of the memory device.
2Quantity of substance
If more word lines are stacked in vertical direction to increase integration density, then storage capacity is improved, but interference among word lines increases causing data reliability to deteriorate
Solution Approach 1:
The patent changes the threshold voltage parameter of ground select transistors based on their specific function and location. By programming first ground select transistors to a lower threshold voltage and second ground select transistors to a higher threshold voltage, the system optimizes the electrical characteristics to minimize interference among vertically stacked word lines while maintaining high storage capacity.
Data Source
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AI summary
A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.