3D NAND String Select Transistor Threshold Tuning for Uniform Erase
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Solution Overview
Problem
Three-dimensional memory devices with multi-hole structures experience performance differences due to intrinsic characteristic variations among channel holes, leading to uneven erase speeds and gate induced drain leakage (GIDL) currents.
Innovation Solution
Incorporating string select transistors with different threshold voltages, where outer transistors have higher threshold voltages than inner transistors, to compensate for uneven erase speeds and minimize GIDL currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If string select lines are positioned at different distances from word line ends, then channel hole performance varies, but this causes uneven erase speeds and GIDL currents
Solution Approach 1:
The patent applies local quality by assigning different threshold voltages to string select transistors based on their specific positions. String select transistors connected to string select lines closer to word line ends are given higher threshold voltages, while those farther away receive lower threshold voltages. This localized differentiation compensates for the performance variations caused by position, ensuring uniform erase speeds and minimizing GIDL currents across all channel holes.
2Reliability
If string select transistors have different threshold voltages, then erase speed uniformity improves, but device complexity increases
Solution Approach 1:
The patent implements parameter changes by modifying the threshold voltage parameter of string select transistors according to their positional characteristics. By adjusting this key electrical parameter, the patent achieves uniform erase operation across channel holes with different intrinsic characteristics, transforming a heterogeneous system into one that operates uniformly through controlled parameter variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent erase speeds across channel holes by adjusting threshold voltages, reducing GIDL currents, and enhancing overall erase operation efficiency.
Implementation Method 1
a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line
Implementation Method 2
An erasing technique for the three-dimensional memory device may include a gate induced drain leakage (GIDL) erasing technique
Data Source
AI summary
A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.