NAND Structure Tier Select Gate Transistors Program Disturb
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Solution Overview
Problem
As semiconductor memory technologies, such as NAND flash memory, face challenges in scaling due to increased variability in transistor characteristics over process, voltage, and temperature, leading to issues like program disturb and reduced reliability, especially as string lengths increase, there is a need for improved methods to enhance performance and reliability.
Innovation Solution
The introduction of tier select gate transistors between memory string tiers in a NAND structure, which can be programmable or non-programmable, with longer channel lengths to reduce short-channel effects and allow for electrical isolation during programming and erase operations, thereby reducing program disturb and enhancing area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If string length is increased to reduce cost per bit, then storage density is improved, but transistor characteristic variability increases leading to program disturb and reduced reliability
Solution Approach 1:
The patent divides the NAND string into multiple segments by inserting isolation transistors between groups of memory cell transistors. This segmentation isolates different portions of the string during programming operations, preventing program disturb from propagating across the entire string while maintaining high storage density through efficient use of the string structure.
Solution Approach 2:
The patent introduces isolation transistors as intermediary elements between memory cell transistors in the NAND string. These isolation transistors act as mediators that can be selectively activated to disconnect different segments of the string during programming operations, thereby preventing harmful electrical interactions while maintaining the overall string functionality for high-density storage.
2Quantity of substance
If process geometry is shrunk to reduce cost per bit, then storage density is improved, but transistor characteristic variability increases
Solution Approach 1:
The patent applies different characteristics to different parts of the transistor structure. Specifically, the isolation transistors have longer channel lengths than the memory cell transistors, providing better electrical isolation and reduced variability in the critical isolation regions while allowing the memory cell transistors to maintain their optimized dimensions for high-density storage.
Solution Approach 2:
The patent changes the channel length parameter of the isolation transistors to be longer than that of the memory cell transistors. This parameter change reduces short-channel effects and variability in the isolation transistors, improving manufacturing precision and reliability without compromising the overall storage density achieved through process geometry scaling.
3Reliability
If longer channel length is used for isolation transistor, then short-channel effects are reduced, but device complexity increases
Solution Approach 1:
The patent segments the NAND string into multiple isolated portions using isolation transistors with longer channel lengths. This segmentation approach manages complexity by creating discrete, controllable sections rather than dealing with the entire string as one complex unit, making the longer channel length design manageable and effective.
Solution Approach 2:
The patent applies longer channel lengths selectively only to the isolation transistors rather than all transistors in the structure. This localized application of the longer channel length reduces short-channel effects where needed (at isolation points) without unnecessarily increasing complexity throughout the entire device structure.
Data Source
AI summary
Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.