3D NAND Top Select Gate Isolation for Critical Dimension Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D NAND semiconductor devices face challenges in patterning top select gate cuts (TSG Cut) due to differences in critical dimensions between first and second top select gate isolation structures, leading to issues during mask patterning and potential damage to the top select gate layer.
Innovation Solution
The semiconductor device features a stack structure with alternately stacked dielectric and conductive layers, including a top select gate layer with first and second top select gate isolation structures, where the insulation portion of the second top select gate isolation structure is divided into substructures to match the critical dimension of the first top select gate isolation structure, thereby avoiding patterning compensation rule discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the insulation portion of the second top select gate isolation structure is kept as a single structure, then the manufacturing process is simpler, but the critical dimension cannot be matched with the first top select gate isolation structure, leading to patterning compensation rule discrepancies and potential damage to the top select gate layer
Solution Approach 1:
The insulation portion of the second top select gate isolation structure is divided into multiple substructures (first, second, third substructures) with different widths. This segmentation allows each substructure to have a specific critical dimension that can be matched with the first top select gate isolation structure, thereby resolving the patterning compensation rule discrepancies while maintaining manufacturing feasibility
Solution Approach 2:
Different substructures of the insulation portion are designed with different local qualities (different widths), where the first substructure has a first width, the second substructure has a second width, and the third substructure has a third width. This local differentiation enables precise critical dimension matching at different locations to ensure proper patterning compensation
2Manufacturing precision
If the insulation portion is divided into multiple substructures with different widths, then the critical dimension matching is achieved, but the structural complexity increases
Solution Approach 1:
The insulation portion is segmented into three distinct substructures with progressively different widths, allowing each segment to serve a specific function in achieving critical dimension matching while maintaining overall structural organization and manufacturability
Solution Approach 2:
The substructures are designed with asymmetric width dimensions (first width, second width, third width), where each width is specifically tailored to achieve the desired critical dimension matching. This asymmetric design enables precise control over patterning compensation rules without requiring overly complex symmetric structures
Data Source
AI summary
A semiconductor device includes a stack structure and channel holes penetrating through the stack structure. The stack structure includes alternately stacked dielectric layers and conductive layers, the conductive layers including a top select gate layer. The top select gate layer is provided with a first top select gate isolation structure and a second top select gate isolation structure, and the channel holes are located between the first top select gate isolation structure and the second top select gate isolation structure. The second top select gate isolation structure includes an insulation portion, and the insulation portion is divided into a plurality of second top select gate isolation substructures, so that the critical dimension (CD) of the second top select gate isolation substructure may be matched with the CD of the first top select gate isolation structure.