3D NAND Memory Cell Transistor Configuration for Channel Resistance Reduction

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Solution Overview

Problem

3D NAND memory cells experience increased channel resistance due to cascode-connected transistors, which degrades the turn-on current, limiting storage density and efficiency.

Innovation Solution

The memory cell is configured with transistors M2_1-M2_a and M4_1-M4_a connected in series, with a common source line, reducing electrical string length and channel resistance by dividing the current path into two parallel paths, thereby maintaining ON state current and ON-OFF window integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If more memory gate films or transistor layers are stacked to increase storage density, then storage density increases, but channel resistance increases and turn-on current degrades

Engineering Contradiction:

Improvestorage densityVSAvoidturn-on current

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The memory device is divided into two separate storage portions (first storage portion and second storage portion) that are stacked vertically. Each storage portion has its own set of transistors and gate films, allowing the current path to be segmented and reducing the cumulative channel resistance while maintaining high storage density through vertical stacking.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar or single-stack configuration to a three-dimensional stacked configuration with two storage portions arranged vertically. This dimensional change allows more storage elements to be packed into a smaller footprint while managing the channel resistance through the specific stacked architecture and shared source line design.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If transistors are connected in series to form memory cells, then storage capacity increases, but channel resistance increases and degrades current flow

Engineering Contradiction:

Improvestorage capacityVSAvoidelectrical string length

Core Design Contradiction:

Quantity of substanceVSLength of moving object

Solution Approach 1:

The electrical path is segmented into two separate storage portions with a shared source line. This segmentation creates multiple current paths that can operate in parallel, effectively reducing the total electrical string length and channel resistance while maintaining the required storage capacity through the combined capability of both storage portions.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11574917B2Method of forming memory device

Publication Date: 2023.02.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming a memory device is provided. The method comprises: forming a first storage portion on a substrate; forming a conductive layer on the first storage portion, wherein the conductive layer has a first surface coupled to the first storage portion; and forming a second storage portion on a second surface of the conductive layer, wherein the second surface is opposite to the first surface.