Vertical NAND Charge Trap Nanostructures for Inter-Cell Retention
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Solution Overview
Problem
The charge retention characteristics of vertical NAND flash memory devices deteriorate due to increased charge mobility between stacked memory cells, which is exacerbated by the miniaturization and high integration of these devices.
Innovation Solution
Incorporating a charge trap layer with nanostructures and a base material in the channel hole, where the nanostructures have a higher trap density and lower band gap than the base, and forming the charge trap layer through spinodal decomposition to enhance charge retention, thereby reducing charge mobility and improving device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased and the heights of stacked memory cells are decreased for miniaturization and high integration, then the integration density is improved, but charge mobility between memory cells increases and charge retention characteristics deteriorate
Solution Approach 1:
The charge trap layer is designed with non-uniform trap density distribution, having higher trap density in specific regions compared to others. This local variation in trap density allows for enhanced charge retention in critical areas while maintaining the overall high integration density structure with multiple stacked memory cells
Solution Approach 2:
The charge trap layer is formed as a composite structure with a base material and nanostructures distributed within it. The base material provides the matrix structure while the embedded nanostructures (such as metal oxides or nitrides) provide additional trap sites, creating a composite material system that enhances charge retention characteristics without increasing the physical height of memory cells
2Reliability
If a charge trap layer with nanostructures and base material is formed through spinodal decomposition, then charge retention characteristics are improved, but manufacturing process complexity increases
Solution Approach 1:
The charge trap layer is formed through spinodal decomposition, which is a phase separation process that occurs when a homogeneous mixture becomes unstable and separates into distinct phases. By controlling the thermal processing conditions, the base material and nanostructure-forming materials spontaneously separate into a composite structure with embedded nanostructures, achieving complex microstructure through a relatively simple phase transition process rather than complex multi-step fabrication
Solution Approach 2:
The formation of the charge trap layer with nanostructures is achieved by changing processing parameters such as temperature and composition ratios during thermal annealing. By adjusting these parameters, the spinodal decomposition process produces the desired nanostructure distribution and size, allowing control over charge retention properties without requiring complex lithography or deposition steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves charge retention characteristics and device uniformity, allowing for higher integration and reduced gaps between conductive layers in the vertical NAND flash memory device.
Implementation Method 1
forming the charge trap layer through spinodal decomposition to enhance charge retention
Data Source
AI summary
A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.