3D NAND Memory Array Trenches for Sub-Block Electrical Coupling
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Solution Overview
Problem
Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architectures, which affect data retention and access performance.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays, where trenches are created between memory-block regions to define laterally-spaced sub-blocks, enabling the formation of vertically-stacked memory cells with conductive and insulative tiers, and channel material strings are formed to ensure electrical connectivity and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trenches are formed to create laterally-spaced sub-block regions before forming trenches between memory-block regions, then manufacturing precision and structural integrity are improved, but device complexity and process steps increase
Solution Approach 1:
The memory array fabrication process is segmented into distinct stages: first forming trenches to create laterally-spaced sub-block regions within each memory block, then subsequently forming trenches between adjacent memory blocks. This segmentation allows each etching operation to be optimized independently, improving precision while managing complexity through systematic process breakdown
Solution Approach 2:
The trenches for creating sub-block regions are formed in advance before the trenches between memory blocks are formed. This preliminary action establishes a stable structural framework that guides subsequent processing steps, ensuring that the memory blocks are properly positioned and aligned before final separation trenches are created
2Reliability
If vertically-stacked memory cells are formed with multiple conductive and insulative tiers, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar memory cell arrangements to vertically-stacked three-dimensional structures. Multiple tiers of conductive and insulative materials are stacked vertically to create memory cells that extend in the vertical dimension, thereby improving electrical connectivity and density without increasing lateral footprint
Solution Approach 2:
The vertically-stacked memory cells utilize composite structures comprising alternating layers of conductive materials (for electrodes and interconnects) and insulative materials (for dielectric layers and isolation). This composite approach enables reliable electrical connectivity while maintaining structural integrity through the coordinated stacking of materials with complementary properties
3Duration of action of stationary object
If channel material strings are formed to connect vertically-stacked memory cells, then data retention is improved, but process complexity increases
Solution Approach 1:
Channel material strings serve as intermediary conductive pathways that connect the vertically-stacked memory cells to the read/write circuitry. These channel strings are formed to extend through the vertical stack, providing reliable electrical conduits for data access while isolating the memory cell arrays from direct connection to control circuitry
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.