NAND Memory Valley Voltage Detection for Bit Flip Correction
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Solution Overview
Problem
The accuracy of reading data stored in NAND memory cells is affected by charge fluctuations due to increased use time and temperature variations, leading to bit flips and data inaccuracies.
Innovation Solution
A memory device and system that adjusts the read voltage based on the number of bit flips detected, determining a valley voltage for accurate data reading through iterative adjustments, using a peripheral circuit or memory controller to optimize read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed repeatedly on NAND memory cells, then data access speed is maintained, but charge stored in memory cells changes due to use time and temperature variations, leading to bit flips and reduced reading accuracy
Solution Approach 1:
The patent implements a feedback mechanism by detecting bit flip rates during read operations and dynamically adjusting the read voltage accordingly. When bit flips are detected, the system modifies the read voltage to compensate for charge variations in memory cells, thereby maintaining reading accuracy despite repeated access operations and temperature variations.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on detected bit flip patterns. By adjusting the read voltage in response to observed errors, the system compensates for charge degradation in memory cells over time and across temperature conditions, resolving the contradiction between maintaining access speed and ensuring reading accuracy.
2Measurement precision
If read voltage is adjusted frequently to correct bit flips, then reading accuracy is improved, but system complexity increases due to iterative adjustments and multiple read operations
Solution Approach 1:
The patent applies partial adjustment by performing iterative read operations only when bit flips are detected, rather than continuously adjusting read voltage. The system performs a limited number of retry reads with adjusted voltages, applying just enough correction to resolve errors without unnecessarily increasing system complexity through constant adjustments.
3Reliability
If multiple read operations with adjusted voltages are performed, then bit flip errors are reduced, but time consumption increases due to iterative adjustments
Solution Approach 1:
The patent performs iterative read adjustments only partially - specifically, only when bit flips are detected during initial reads. The system limits the number of retry operations and voltage adjustment iterations, applying corrections just sufficient to recover data integrity while minimizing additional time consumption compared to continuous or excessive retry mechanisms.
Data Source
AI summary
According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.