NAND Memory Valley-Voltage Read Control for Bit-Flip Errors
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Solution Overview
Problem
The accuracy of reading data stored in NAND memory cells is affected by changes in stored charge due to increased use time and temperature variations, leading to high read errors that exceed Error Correction Code (ECC) correction capabilities.
Innovation Solution
A method involving multiple adjustments to the read voltage to determine a 'valley voltage' based on the relationship between the number of flipped bits and a preset value, optimizing the read operation by using this voltage for improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed read voltage is used for reading data from NAND memory cells, then the read operation is simple and fast, but the read accuracy deteriorates due to charge changes from use time and temperature variations
Solution Approach 1:
The patent implements dynamic read voltage adjustment by introducing a read voltage adjustment module that modifies the read voltage based on detected error patterns. The system transitions from a fixed read voltage approach to a dynamic one where the voltage is adapted in real-time according to the actual read conditions and error characteristics, thereby maintaining high read accuracy across varying usage conditions without excessive complexity
Solution Approach 2:
The patent employs feedback mechanisms where the read result is analyzed to detect flipped bits, and this information is fed back to adjust the read voltage for subsequent reads. The read voltage adjustment module uses the error detection results to modify the voltage level, creating a closed-loop system that continuously optimizes read accuracy based on actual performance
2Measurement precision
If read voltage is adjusted multiple times to improve accuracy, then the read accuracy improves, but the read time increases
Solution Approach 1:
The patent applies partial adjustment by introducing a threshold mechanism for the number of flipped bits. When the number of flipped bits exceeds a predefined threshold, the read voltage adjustment is triggered; otherwise, the original read voltage is maintained. This selective approach avoids unnecessary voltage adjustments and associated time delays while still correcting significant read errors
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on detected error conditions. By modifying the voltage level in response to flipped bit patterns and using threshold-based decision logic, the system achieves high read accuracy without requiring multiple sequential reads, thereby minimizing the time penalty
3Reliability
If error correction is performed extensively to handle read errors, then the data reliability improves, but the processing time increases
Solution Approach 1:
The patent performs preliminary error detection and read voltage adjustment before final data processing. By detecting flipped bits early in the read process and adjusting the voltage proactively, the system prevents many errors from propagating to the error correction stage, thereby reducing the burden on ECC processing and minimizing overall processing time
Data Source
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Figure 2b~3a
Figure 3b~4
AI summary
Examples of the present application disclose a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells comprising multiple memory cells, a preset number of the memory cells forms one code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first state corresponding to the code words at a current read voltage; the first state is to represent a relationship of size between the number of bits in the code words which are flipped in two results of reading at the corresponding reading voltage and the voltage near the corresponding reading voltage and a first preset value; perform multiple adjustments to the current read voltage, and obtain a first state corresponding to the code words at the read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a variation trend of the relationship of size between the number of flipped bits and the first preset value indicated by a plurality of the obtained first states, the valley voltage is to be a read voltage for performing a read operation on the code words.