NAND Memory Valley Voltage Selection for Reliable Page Reads
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Solution Overview
Problem
The reliability of data reading in NAND memories is compromised due to variations in stored charges over time and temperature, leading to increased read errors beyond the capability of existing error correction mechanisms.
Innovation Solution
A memory device and system that utilize a predicted initial read voltage and a target valley voltage to improve read accuracy by considering the position of word lines and blank physical pages, reducing the need for iterative loop corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed read voltage is used for reading code words in NAND memory, then the device complexity is low and operation is simple, but read accuracy deteriorates due to charge variations over time and temperature
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal read voltages in a lookup table based on word line positions and blank physical page positions before actual read operations. This pre-computation approach eliminates the need for complex real-time voltage adjustment mechanisms while maintaining high read accuracy, as the voltage selection is directly retrieved from pre-stored data based on position parameters.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read voltage parameter based on two key parameters: the position of the word line in the open block and the position of the first blank physical page. The read voltage is selected from multiple predetermined voltage levels corresponding to different position combinations, allowing the system to adapt to charge variations without complex circuitry.
2Reliability
If iterative loop corrections are performed to correct read errors, then read accuracy is improved, but the time required for error correction increases
Solution Approach 1:
The patent applies preliminary action by pre-determining the optimal read voltage before the actual read operation based on word line position and blank physical page position. This prevents read errors from occurring in the first place by using the correct voltage from the start, thereby eliminating or reducing the need for subsequent iterative error correction loops and significantly reducing error correction time.
Solution Approach 2:
The patent implements feedback by using the positions of word lines and blank physical pages as feedback parameters to select appropriate read voltages. This position-based feedback mechanism allows the system to adaptively choose the optimal voltage for each specific read operation, ensuring high reliability while minimizing the need for time-consuming error correction iterations.
3Measurement precision
If read voltage is adjusted based on word line position and blank physical page position, then read accuracy is enhanced, but the complexity of voltage control increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the optimal read voltage values in a lookup table based on all possible combinations of word line positions and blank physical page positions. During actual operation, the system simply queries this pre-computed table using the current position parameters, which maintains operational simplicity while achieving high voltage accuracy without complex real-time computation.
4Measurement precision
If higher read voltages are used to ensure accurate reading of degraded charges, then read accuracy is improved, but more errors are introduced due to voltage sensitivity
Solution Approach 1:
The patent implements parameter changes by selecting from multiple predetermined read voltage levels based on the specific position parameters (word line position and blank physical page position). Instead of using a single high voltage that may cause errors, the system dynamically adjusts the voltage parameter to the optimal level for each specific read operation, thereby achieving accurate reading of degraded charges without introducing voltage-induced errors.
Data Source
Figure 1~2A
Figure 2B~3
Figure 4~5
AI summary
Examples of the present application disclose a memory device including: a memory cell array including a plurality of blocks, wherein the blocks includes a plurality of word lines, and a plurality of memory cells coupled to the plurality of word lines, the plurality of memory cells coupled to a same word line form a physical page, and a physical page comprises one or more code words; and a peripheral circuit coupled to the memory cell array and configured to: acquire a predicted initial read voltage of the code words according to a position of the word line coupled to the code words in an open block and a position of a first blank physical page in the open block; and obtain a target valley voltage of the code words according to a first result corresponding to the code words at the predicted initial read voltage.