NAND Memory Valley Voltage Prediction for Accurate Reads
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Solution Overview
Problem
The charge stored in NAND memory cells is prone to change over time and with repeated read operations, leading to reduced reading accuracy due to shifts in threshold voltage, which can result in reading errors that exceed the capability of existing error correction methods.
Innovation Solution
A memory device and system that utilize a peripheral circuit to obtain multiple read results under varying read voltages, apply a preset function model to predict a target valley voltage, and use this voltage for accurate data reading, thereby reducing the need for time-consuming trial-and-error methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional read voltage methods are used, then the reading process is simple, but reading accuracy deteriorates due to charge changes over time and repeated read operations
Solution Approach 1:
The patent applies preliminary action by pre-establishing a function model that describes the relationship between read voltage and first results (number of flipped bits). Before actual reading operations, the system obtains multiple first results under different reference read voltages, fits a function model (e.g., quadratic function), and predicts the valley voltage in advance. This preliminary modeling eliminates the need for trial-and-error voltage adjustments during reading, thereby improving reading accuracy without significantly increasing operational complexity.
Solution Approach 2:
The patent implements feedback by using the first results (number of flipped bits) obtained from reading operations to continuously update and refine the function model. The system monitors how the number of flipped bits changes with different read voltages and uses this feedback information to adjust the predicted valley voltage, ensuring the read process adapts to charge changes over time and maintains high reading accuracy.
2Measurement precision
If trial-and-error methods are used to determine optimal read voltage, then reading accuracy can be maintained, but response time increases significantly
Solution Approach 1:
The patent eliminates trial-and-error methods by performing preliminary fitting of the function model during manufacturing or initial operation. The valley voltage is predicted in advance using the pre-established function model, allowing the system to directly apply the optimal read voltage without iterative adjustments, thereby dramatically reducing response time while maintaining reading accuracy.
Solution Approach 2:
The system performs self-service by autonomously determining the optimal read voltage through the function model without requiring external intervention or repeated testing. The peripheral circuit automatically obtains first results, fits the model, predicts the valley voltage, and applies it for reading operations, making the entire process self-contained and efficient.
3Reliability
If multiple read voltages are tested to ensure accuracy, then reading reliability improves, but the number of operations and time consumption increase
Solution Approach 1:
The patent changes the parameter approach from testing multiple discrete voltage values to using a continuous function model that predicts the optimal voltage. Instead of systematically testing multiple read voltages to ensure reliability, the system uses the function model to directly calculate the valley voltage based on the relationship between read voltage and first results, thereby maintaining reliability while improving operational efficiency.
Solution Approach 2:
The patent replaces the mechanical trial-and-error voltage testing system with a mathematical function model. Instead of physically testing multiple voltage levels through repeated operations, the system uses mathematical fitting and prediction to determine the optimal read voltage, substituting computational methods for physical experimentation and thereby improving productivity.
Data Source
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AI summary
Examples of the present application discloses a memory device, an operation method thereof, a memory system, a memory controller and a storage medium. The memory device includes: a memory cell array including a plurality of memory cells, wherein a preset number of memory cells form a code word; a peripheral circuit coupled to the memory cell array and configured to: obtain M first results of at least one code word under M reference read voltages, wherein the first result comprises a number of the bits which represents the number of flipped bits of the at least one code word in two read results under a first read voltage and a second read voltage and M is an integer larger than or equal to 2; obtain a predicted valley voltage according to the M first results within a first preset interval and the M reference read voltages in combination with a preset function model representing the relationship between the first results and the reference read voltages; and based on the predicted valley voltage, determine a target valley voltage; the target valley voltage is configured as a read voltage used when a read operation is performed on the at least one code word.