NAND Variable-Resistance Memory Cell Structure for Scalability
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Solution Overview
Problem
Current variable-resistance material random-access memory structures face challenges in miniaturization due to the isolation of individual memory cells, which complicates circuit design and limits the scalability of memory arrays.
Innovation Solution
The proposed solution involves a semiconductor device structure with shallow-trench isolation and the use of variable-resistance materials like gallium, germanium, indium, antimony, and tellurium-based phase-change random-access memory cells, where each cell is accessed by a select gate and controlled by parallel control gates, eliminating the need for a top electrode and metallization layer, allowing for block write or erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If individual memory cells are isolated using conventional structures with multiple metal layers, then each cell can be independently accessed, but the device complexity and number of required metal layers increase
Solution Approach 1:
The patent merges the functions of multiple metal layers into a single metallization layer by using control gates that extend from the channel region to serve as both control and selection functions. This consolidation reduces the number of required metal layers while maintaining the ability to independently access individual memory cells through the variable resistance state of the channel.
Solution Approach 2:
The control gates are designed to perform multiple functions: they serve as both control gates for enabling current flow and as selection lines for accessing specific memory cells. This multi-functionality eliminates the need for separate selection metal layers, reducing overall device complexity while preserving independent cell access capability.
2Productivity
If more metal layers are used to access individual memory cells in parallel, then programming and reading capabilities are enhanced, but the area occupied by circuitry increases
Solution Approach 1:
The patent transitions from a planar arrangement requiring multiple metal layers stacked vertically to a three-dimensional structure where control gates extend vertically from the channel region. This dimensional change allows multiple control gates to access the same channel region without requiring additional horizontal metal layers, thereby enhancing programming and reading capabilities while minimizing the increase in circuitry area.
Solution Approach 2:
The control gates are positioned to overlap with and extend beyond the channel region, creating a nested configuration where the control gate structure encompasses the channel. This nesting allows the control gates to be integrated within the vertical profile of the device rather than requiring additional lateral space, reducing the overall circuitry footprint.
3Ease of operation
If conventional memory cell isolation structures are used, then individual cell addressing is achieved, but heat loss increases during programming operations
Solution Approach 1:
The patent extracts the selection function from separate metal layers and integrates it into the control gate structure itself. By taking out the selection functionality and combining it with the control gate, the device reduces the number of current paths and resistance interfaces, thereby minimizing heat loss during programming operations while maintaining individual cell addressing capability.
4Ease of operation
If multiple metal layers including top-electrode selection lines are used, then memory cell selection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the top-electrode selection line function into the control gate structure, eliminating the need for separate selection metal layers. This consolidation simplifies the manufacturing process by reducing the number of metallization steps and material depositions required, while the control gate's extended structure continues to provide effective memory cell selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient programming and reading of multiple memory cells in a single operation, reduces programming current requirements, and minimizes heat loss, facilitating the creation of larger memory arrays with improved contact integrity and reduced complexity.
Implementation Method 1
gallium, germanium, indium, antimony, and tellurium-based phase-change random-access memory cells
Data Source
AI summary
A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells is in parallel with a corresponding series of control gates. A select gate is also in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell includes turning off the corresponding control gate, while turning on all other control gates. Devices include the variable-resistance material memory array.