3D NAND Verification Window Control for Faster MLC Programming
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Solution Overview
Problem
In 3D NAND flash memory devices, the increasing number of program loops and verification operations prolongs the programming time, especially with multi-level cells (MLCs) that require more verification states, leading to inefficiencies and performance issues.
Innovation Solution
A method for programming memory devices that determines the start and end points of verification operations based on the number of program loops used to reach a target state, allowing for the skipping of verification sections in subsequent program loops, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of verification operations is increased to ensure accurate programming of MLCs, then the programming reliability is improved, but the programming time increases significantly
Solution Approach 1:
The patent applies partial verification by determining a specific verification start point and end point within the program loops, rather than performing verification in every loop. This partial action approach verifies only the critical portions of programming, reducing the total number of verification operations while maintaining sufficient programming reliability for MLCs.
Solution Approach 2:
The patent segments the verification process by dividing it into specific start and end points within the program loops. This segmentation allows verification to be performed only in the necessary range rather than continuously throughout all program loops, thereby reducing verification time while maintaining reliability.
2Manufacturing precision
If the number of program loops is increased to achieve precise threshold voltage adjustment for multiple program states, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent performs verification only partially during program loops by establishing a verification start point and end point. This partial verification approach maintains precise threshold voltage adjustment for multiple program states while reducing the overall verification burden, thereby improving programming speed without sacrificing precision.
Solution Approach 2:
The patent dynamically adjusts verification parameters (start point and end point of verification) based on programming progress and requirements. This parameter change allows the system to maintain high precision for threshold voltage adjustment while adapting verification intensity to actual needs, improving overall productivity.
3Measurement precision
If verification operations are performed in every program loop to monitor programming progress, then the measurement precision is improved, but the loss of time increases
Solution Approach 1:
The patent performs verification only partially by determining specific start and end points within program loops rather than verifying in every loop. This partial verification maintains sufficient measurement precision for detecting programming state changes while significantly reducing the time consumed by verification operations.
Solution Approach 2:
The patent performs preliminary determination of verification start and end points before executing verification operations. This preliminary action allows the system to plan verification strategically, ensuring measurement precision is maintained only where necessary while avoiding redundant verification time.
Data Source
AI summary
A memory device and a method for programming the same may include, applying program loops to a plurality of memory cells of the memory device to adjust threshold voltages of the plurality of memory cells to desired target states, each of the program loops including a program section and a verification section, programming the memory cells of a first page, storing a number of first program loops used to complete the programming of the memory cells of the first page to a first target state, programming the memory cells of a second page to the first target state, the second page adjacent to the first page, and performing a verification operation on the second page.