NAND Program Verify Staggering for Peak Current Control
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Solution Overview
Problem
Conventional power management techniques in NAND memory devices, such as predictive peak power management (pPPM), while effective in managing power consumption, lead to performance degradation and throughput issues due to delayed operations, and alternative methods like 1P0V schemes compromise data integrity and may cause uncorrectable errors.
Innovation Solution
Staggering program verify operations across different sub-blocks within NAND memory device dies to avoid simultaneous peak current consumption, thereby reducing the likelihood of triggering power management throttling and maintaining operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program verify operations are performed simultaneously on all NAND dies, then programming speed and throughput are improved, but peak instantaneous current consumption increases triggering power management throttling
Solution Approach 1:
The patent segments the program verify operations across multiple NAND dies by assigning different verify operations to different dies. Instead of performing all verify operations simultaneously on all dies, the system divides the workload so that each die performs verify operations on specific sub-blocks at different times, thereby segmenting the peak current consumption across time and preventing simultaneous power spikes that would trigger power management throttling.
2Power
If predictive peak power management algorithms are used to stagger operations, then power consumption is managed, but performance degradation occurs due to delayed operations
Solution Approach 1:
The patent applies preliminary action by pre-configuring the staggered verify operation schedule before the programming sequence begins. The controller pre-determines which dies will perform verify operations on which sub-blocks and in what order, allowing the system to manage power consumption effectively while maintaining optimal performance. This preliminary planning avoids the need for real-time power management interventions that would cause delays and performance degradation.
3Power
If program verify operations are delayed to manage power, then peak current consumption is reduced, but operational efficiency and throughput decrease
Solution Approach 1:
The patent implements dynamics by creating a flexible, adaptive verify operation schedule that can be adjusted based on the specific programming workload and power constraints. The system dynamically assigns verify operations to different dies and sub-blocks based on current conditions, allowing it to optimize both power consumption and operational efficiency for each programming sequence rather than using fixed delays that would always reduce throughput.
Data Source
AI summary
A processing device configures a memory device such that program verify operations are performed for each die of the memory device on different sub-blocks. In configuring the memory device, the processing device configures a first die for performance of program verify operations on a first sub-block within the first die and configures a second die for performance of program verify operations on a second sub-block within the second die. The processing device initiates a programming sequence to write data to the memory device based on the configuring of the memory device. The programming sequence comprises performance of a first program verify operation on the first sub-block within the first die prior to performance of a second program verify operation on the second sub-block within the second die.