3D NAND Program Verify Shift for Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional NAND memory arrays, data retention is compromised due to tier-pitch scaling, which lowers the ultraviolet threshold voltage (UVVt) and results in excessive degradation, with existing methods failing to effectively raise UVVt, necessitating a shift in the operating window by extending negative read voltages.
Innovation Solution
The solution involves leveraging word line-to-cell coupling to adjust the program verify voltage levels during programming, specifically lowering the effective program verify voltage for level L1 (PV1C) by 500-700 mV using a dedicated, trimmable voltage source or alternative power sources like VCC or GND, to compensate for word line-to-word line interference and cell-to-cell coupling, thereby enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tier-pitch scaling is implemented to increase memory density, then storage capacity is improved, but ultraviolet threshold voltage degrades excessively compromising data retention
Solution Approach 1:
The patent changes the voltage parameter by applying a negative pass voltage to the non-selected word line during program verify operations. This shifts the effective program verify level downward, compensating for the degraded UVVt caused by tier-pitch scaling and enabling reliable data retention at higher memory densities.
2Reliability
If negative read voltages are extended to shift the operating window, then data retention is improved, but voltage source complexity increases
Solution Approach 1:
The patent makes the existing pass voltage source multi-functional by using it for both read operations and program verify operations. This eliminates the need for a separate negative voltage source, maintaining data retention improvement while avoiding additional voltage source complexity.
3Reliability
If program verify voltage levels are lowered to compensate for interference, then data retention is improved, but voltage source range requirements increase
Solution Approach 1:
The patent changes the operating parameter by introducing a negative pass voltage that shifts the effective program verify level. This allows the existing voltage source to operate within its available range while achieving the required lower effective verify level through the superposition of the negative pass voltage on the selected word line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively shifts down the program verify voltage levels, improving data retention in QLC NAND memory by compensating for interference, ensuring reliable operation even with scaled tier pitches.
Implementation Method 1
The solution involves leveraging word line-to-cell coupling to adjust the program verify voltage levels during programming
Data Source
AI summary
A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and-apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line, apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.