NAND VGS Ladder for Accurate In-Memory Compute
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Solution Overview
Problem
Existing artificial neural networks are computationally intensive due to the need for extensive data transfers of weights between memory and processing units, and the precision of gate-to-source voltage in NAND memory cell transistors is not accurately accounted for, affecting computation accuracy.
Innovation Solution
Implementing a VGS ladder technique that estimates and adjusts the source terminal voltage of NAND memory cell transistors during in-memory computing, ensuring the actual gate-to-source voltage is closer to the target, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional neural network computation is implemented with separate memory and processing units, then data transfer between memory and processing units occurs, but computational intensity and data transfer requirements become extremely high
Solution Approach 1:
The patent merges memory and processing functions by implementing neural network computations directly within the memory array. Memory cells store weights and perform analog multiplication with input signals, eliminating the need to transfer weights between separate memory and processing units. This in-memory computing approach combines storage and computation in a single location, dramatically reducing data transfer requirements and energy consumption.
2Measurement precision
If NAND memory cell transistors are used for in-memory computing, then computational operations are performed, but gate-to-source voltage precision is not accurately accounted for, affecting computation accuracy
Solution Approach 1:
The patent applies preliminary compensation by estimating the source terminal voltage for each NAND memory cell before performing the computational operation. These estimated source voltages are used to pre-adjust the gate voltages, ensuring that the actual gate-to-source voltage during computation matches the intended target voltage. This preliminary voltage adjustment compensates for variations in source terminal voltage, thereby improving computation accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the estimated source terminal voltage is fed back into the gate voltage determination process. The system continuously monitors and adjusts gate voltages based on the estimated source voltage conditions, creating a closed-loop control system that maintains accurate gate-to-source voltage despite variations in the memory cell operating conditions.
Data Source
AI summary
Technology for NAND in-memory compute. A NAND memory system uses a VGS ladder in which the expected (or estimated) voltage at the source terminal of a particular NAND memory cell transistor is factored into the determination of the voltage to apply to the gate. An estimate may be made of what voltage will be at the source terminal of each NAND memory cell transistor during in-memory computation. The voltage to apply to the gate of the NAND memory cell transistor may then be determined by adding the estimated source terminal voltage to the target VGS. Therefore, the actual VGS is much closer to the target VGS thereby improving accuracy of NAND in-memory compute.