3D NAND Memory Cell Voltage Adjustment for Threshold Consistency
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Solution Overview
Problem
3-dimensional semiconductor memory devices face challenges in maintaining consistent threshold voltage characteristics during erase verify and read operations, leading to degradation over program/erase cycles and read operations due to variations in memory cell locations.
Innovation Solution
A semiconductor memory device with a memory cell array comprising strings of drain select, pipe, and source select transistors, along with a peripheral circuit and control logic that adjusts operation voltages based on the distance between memory cells and the pipe transistor during erase verify and read operations, ensuring uniform threshold voltages and reducing disturb phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3-dimensional semiconductor memory device uses vertically formed strings with memory cells at different locations, then the degree of integration is improved, but the threshold voltage characteristics become inconsistent due to location variations
Solution Approach 1:
The patent applies local quality by adjusting the verify voltage level based on the specific location of the selected memory cell within the string. Memory cells at different positions (e.g., adjacent to pipe transistor vs. far from pipe transistor) receive different verify voltage levels to compensate for location-induced threshold voltage variations. This ensures consistent verification accuracy across all cell positions while maintaining the high integration benefits of 3D vertical strings.
2Device complexity
If the verify voltage level is kept constant for all memory cells, then the device complexity is reduced, but the threshold voltage characteristics degrade over program/erase cycles due to location variations
Solution Approach 1:
The patent implements dynamic verify voltage control where the verify voltage level is adjusted based on the position of the selected memory cell within the string. Instead of using a fixed verify voltage for all cells, the control logic dynamically selects appropriate voltage levels (e.g., higher verify voltage for cells far from pipe transistor, lower verify voltage for cells adjacent to pipe transistor). This dynamic adjustment maintains reliable threshold voltage characteristics throughout program/erase cycles while accounting for location-specific effects.
3Manufacturing precision
If different verify voltage levels are applied to memory cells at different locations, then the threshold voltage characteristics are improved, but the device complexity increases due to additional voltage control mechanisms
Solution Approach 1:
The patent segments the memory cell string into different regions based on position relative to the pipe transistor. Memory cells are divided into groups (e.g., first group adjacent to pipe transistor, second group farther from pipe transistor), with each group receiving a specific verify voltage level. This segmentation approach simplifies the control mechanism compared to fully individualized control, as it groups cells with similar electrical characteristics together while still achieving location-based optimization.
4Ease of operation
If a standard read voltage is applied to all memory cells, then the operation is simple, but read disturb phenomena increase due to variations in memory cell locations
Solution Approach 1:
The patent applies local quality to read operations by adjusting the read voltage level based on the position of the selected memory cell within the string. Cells at different locations (e.g., adjacent to pipe transistor vs. far from pipe transistor) receive different read voltage levels to compensate for location-induced effects. This reduces read disturb phenomena in non-selected cells while maintaining simple read operation protocols through automated voltage selection based on cell position.
Data Source
AI summary
Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed.