NAND Wafer Surface-Mounted Driver Chiplets
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Solution Overview
Problem
Conventional stacked NAND memory designs do not achieve optimal density due to the limited space occupied by bitlines and wordlines, leading to inefficiencies in semiconductor packaging and increased costs.
Innovation Solution
A microelectronic package design featuring a substrate with a NAND wafer coupled to bitline and wordline driver chiplets, where the driver chiplets are elongated and mounted directly to the NAND wafer without adhesives, allowing for a more compact and efficient arrangement of wire bonds and chiplets within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional stacked NAND memory designs are used with discrete logic sections, then the package structure is simplified, but the density is not optimal due to limited space utilization
Solution Approach 1:
The patent segments the driver functionality into separate chiplets (bitline driver chiplet and wordline driver chiplet) that are mounted on the NAND wafer surface. This segmentation allows independent optimization of each driver function while maximizing space utilization on the wafer, resolving the contradiction between simplified package structure and optimal density.
Solution Approach 2:
The patent transitions from a vertical stacking approach to a surface-mounted approach, utilizing the two-dimensional surface area of the NAND wafer. By mounting driver chiplets on the wafer surface rather than stacking them vertically, the design achieves better space utilization and density while maintaining structural simplicity.
2Ease of operation
If bitlines and wordlines occupy more space in conventional designs, then complete driver functionality is achieved, but the overall density decreases
Solution Approach 1:
The patent extracts the driver functionality from the bulk wafer area and places it in separate chiplets mounted on the wafer surface. This extraction allows the bitlines and wordlines to occupy only the minimum necessary space for their function, while the driver chiplets are positioned in peripheral areas, thereby maximizing overall density without compromising driver functionality.
Solution Approach 2:
The driver chiplets act as intermediaries between the control logic and the NAND memory array. By introducing these intermediate components mounted on the wafer surface, the patent enables complete driver functionality while minimizing the space occupied by bitlines and wordlines within the memory array itself.
3Ease of manufacture
If adhesive materials are used to mount chiplets, then the mounting process is simplified, but material usage increases and density decreases
Solution Approach 1:
The patent employs self-aligning mounting features on the driver chiplets that enable direct attachment to the NAND wafer without requiring adhesive materials. The chiplets include integrated alignment structures and mechanical attachment features that facilitate self-service mounting, eliminating the need for additional adhesive materials and improving density.
Data Source
AI summary
A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.