NAND Block Wear Compensation via Local Programming Adjustments
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Solution Overview
Problem
Memory devices face limited lifespans due to wear and tear, leading to premature retirement of blocks, especially when the program/erase count exceeds a threshold, as existing techniques do not effectively manage degradation across different regions within a memory block.
Innovation Solution
The system adapts by changing the programming technique for regions more susceptible to wear, using a smaller program voltage step size and reducing the number of bits per cell in these regions once the program/erase count exceeds a threshold, while maintaining the original technique for less degraded areas, thereby extending the overall life of the memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform programming technique is applied to all regions of a memory block, then the programming process is simple to manage, but regions more susceptible to wear experience premature degradation and the block must be retired early
Solution Approach 1:
The memory block is divided into multiple regions based on wear susceptibility characteristics. Different programming techniques are applied to different regions, allowing tailored management of degradation patterns while extending overall block lifespan.
Solution Approach 2:
The patent applies different programming techniques to different regions of the memory block based on their specific wear characteristics. Regions more susceptible to wear receive different treatment than less susceptible regions, optimizing reliability without requiring complete block retirement.
2Duration of action of stationary object
If the program voltage step size is reduced to compensate for degradation, then the useful life of degraded regions is extended, but the programming speed and productivity decrease
Solution Approach 1:
The memory block is segmented into regions with different wear characteristics, allowing different program voltage step sizes to be applied to different regions. This enables extended useful life in degraded regions without sacrificing programming speed in healthier regions.
Solution Approach 2:
The patent dynamically adjusts the program voltage step size parameter based on the wear state of different regions. By changing this parameter adaptively, the system extends the useful life of degraded regions while maintaining optimal programming performance in less degraded areas.
3Reliability
If the program/erase count threshold is used to retire memory blocks, then wear management is simple, but blocks are retired prematurely due to uneven degradation across regions
Solution Approach 1:
The memory block is divided into multiple regions that can be independently managed based on their wear characteristics. This segmentation allows the system to continue using less degraded regions even when some regions reach their wear threshold, preventing premature complete block retirement.
Solution Approach 2:
Different wear management strategies are applied to different regions based on their degradation patterns. Regions with lower wear can continue to be utilized while regions with higher wear receive protective measures, optimizing overall block utilization beyond simple threshold-based retirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach extends the useful life of memory blocks by compensating for degradation in high-wear regions while maintaining performance in less degraded areas, effectively managing wear across the block.
Implementation Method 1
The charge-trapping material is separated from a channel layer by a tunneling layer
Data Source
AI summary
Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.