NAND Conductive Level Structure for Efficient Wordline Routing
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Solution Overview
Problem
Current NAND memory devices face challenges in efficiently routing electrical signals due to the lack of uniform metal-containing composition in their conductive structures, which affects the performance and efficiency of memory operations.
Innovation Solution
The implementation of conductive levels with two different conductive structures, where one is proximate to the channel material with a conductive liner and the other is distal with a uniform metal-containing composition throughout its vertical thickness, serving as control gates and wordlines respectively, to enhance signal routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NAND memory devices use non-uniform metal-containing composition in conductive structures, then manufacturing complexity is reduced, but signal routing efficiency deteriorates
Solution Approach 1:
The conductive level is segmented into two distinct structures: control gates with liner+core composition and wordlines with uniform composition. This segmentation allows each structure to be optimized independently for its specific function, improving overall signal routing efficiency while managing complexity through functional separation
Solution Approach 2:
Different regions of the conductive level are assigned different metal-containing compositions based on local functional requirements. Control gates proximate to channel material use liner+core composition for optimal transistor control, while distal wordlines use uniform composition for efficient signal distribution, achieving local optimization throughout the device
2Reliability
If uniform metal-containing composition is used throughout conductive rails, then signal routing efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the conductive level into control gates and wordlines, the manufacturing process can apply different composition requirements to each segment. Wordlines require uniform composition for signal routing, while control gates use liner+core structure for transistor control, allowing precision requirements to be matched to functional needs
Solution Approach 2:
The conductive liner is formed preliminarily before the core material in control gates, creating a template that guides subsequent material deposition. This preliminary action ensures proper composition distribution in control gates while allowing uniform material deposition in wordline regions, managing manufacturing precision requirements
3Reliability
If conductive liner and core materials are used in control gates, then electrical signal control improves, but device complexity increases
Solution Approach 1:
The liner+core composition is applied locally only to control gates where it provides optimal electrical signal control for transistor operation. Wordlines use simpler uniform composition, so the complexity benefit is localized to where it is most needed while maintaining overall device functionality
Solution Approach 2:
The dual-composition approach in control gates serves multiple functions: the liner provides adhesion and interface control with the channel material, while the core provides the primary conductive path. This multi-functionality justifies the increased local complexity by delivering superior electrical signal control
Data Source
AI summary
Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.