Word Line Read Voltage Durations for NAND Page Read Speed
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Solution Overview
Problem
Existing memory devices, particularly NAND flash memories, face inefficiencies in read operations due to fixed and prolonged durations for applying read voltages, which hinder performance and speed, especially in high-density storage scenarios.
Innovation Solution
The application of variable durations for read voltages based on the magnitude of voltage differences, allowing precise determination of read durations for each page, thereby optimizing the read operations in NAND flash memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed and prolonged durations are used for applying read voltages, then reliability of read operations is improved, but read speed and performance deteriorate
Solution Approach 1:
The patent applies dynamic adjustment of read voltage duration based on voltage difference magnitude. The peripheral circuit determines different duration values (first duration, second duration, etc.) corresponding to different voltage difference ranges, replacing the conventional fixed duration approach. This dynamic adaptation allows the system to use shorter durations when voltage differences are large (ensuring sufficient signal margin) and longer durations when voltage differences are small (maintaining read reliability), thereby resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the time parameter (duration of read voltage application) based on the voltage difference parameter. By establishing a mapping between voltage difference magnitude and optimal duration, the system adapts the temporal characteristic of the read operation to the electrical conditions, achieving both fast reads when possible and reliable reads when necessary.
2Reliability
If fixed and prolonged durations are used for applying read voltages, then read completeness is improved, but overall read duration and energy consumption increase
Solution Approach 1:
The patent segments the read operation into multiple stages, each with its own optimized duration. Instead of applying a single prolonged voltage to all pages, the system divides pages into groups and applies different duration values (first duration for some pages, second duration for others, third duration for remaining pages). This segmentation allows the total read duration to be reduced while maintaining completeness for each page group.
Solution Approach 2:
The patent applies partial action by using different duration levels for different page groups. Rather than uniformly applying the maximum necessary duration to all pages, the system applies longer durations only to page groups that require them (based on voltage difference characteristics) and shorter durations to others, achieving read completeness for critical pages while minimizing overall time loss.
3Productivity
If variable durations are applied based on voltage differences, then read efficiency is improved, but control complexity increases
Solution Approach 1:
The patent performs preliminary determination of duration values before actual read operations. The peripheral circuit pre-establishes the mapping between voltage difference ranges and duration values, and determines which duration to apply for each page group in advance. This preliminary action simplifies the control logic during execution, as the system only needs to follow the pre-determined duration assignment rather than making complex real-time decisions, thus improving efficiency without excessive complexity.
Solution Approach 2:
The patent introduces an intermediary mechanism (the peripheral circuit's duration determination logic) that mediates between the voltage difference characteristics and the read operation parameters. This intermediary layer abstracts the complexity by implementing a predefined mapping strategy, shielding the rest of the system from complex control decisions while enabling efficient variable duration application.
Data Source
AI summary
The present disclosure provides a memory device, operation method thereof, memory system and operation method thereof. The memory device includes a peripheral circuit and a memory cell array coupled with the peripheral circuit. The memory cell array includes groups of memory cells, and one group of memory cells is correspondingly coupled with one word line. The peripheral circuit is configured to: apply a first read voltage to a selected word line in a first duration, to perform a read operation on a first page of memory cells to be read; and apply a second read voltage to the selected word line in a second duration, to perform a read operation on a second page of the memory cells to be read. A relationship of length between the first duration and the second duration is related to a relationship of magnitude between a first voltage difference and a second voltage difference.