Multi-Material NAND Wordlines for Conductivity and Adhesion
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Solution Overview
Problem
Current NAND memory architectures face limitations in optimizing the performance and efficiency of conductive structures, such as wordlines, which are typically made from a single material, leading to suboptimal conductivity, adhesion, and stress issues.
Innovation Solution
Incorporating conductive regions with three or more different materials, including a core material for low resistance, an intermediate material for adhesion and grain growth promotion, and an outer material for high work function and adherence to dielectric-barrier materials, to enhance conductivity and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single material is used for conductive structures, then manufacturing simplicity is maintained, but conductivity and adhesion performance are suboptimal
Solution Approach 1:
The patent applies composite materials by constructing conductive structures with multiple distinct materials arranged in specific configurations. The conductive structure includes a first material (e.g., tungsten) providing low resistance, a second material (e.g., cobalt) providing adhesion and grain growth promotion, and a third material (e.g., titanium nitride) providing high work function and dielectric barrier adhesion. This multi-material composite approach resolves the contradiction by achieving superior conductivity and adhesion performance while managing the increased material composition complexity through systematic material selection and arrangement.
Solution Approach 2:
The patent applies local quality by assigning different materials to different regions of the conductive structure based on specific functional requirements. The core region uses low-resistance material for optimal conductivity, the intermediate region uses adhesion-promoting material for grain growth, and the outer region uses high work function material for dielectric barrier adhesion. This spatial differentiation of material properties resolves the contradiction by optimizing local performance characteristics without requiring the entire structure to compromise for manufacturing simplicity.
2Reliability
If conductive structures use optimized multi-material composition, then conductivity and adhesion are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the conductive structure into distinct material regions that can be deposited and processed separately. The conductive structure is segmented into a first material region, a second material region, and a third material region, each with specific thicknesses and properties. This segmentation enables optimized manufacturing by allowing independent deposition control, thickness optimization, and process parameter tuning for each material layer, thereby improving conductivity and adhesion while managing fabrication complexity through modular processing.
3Productivity
If single-material conductive structures are used, then stress management is simpler, but operational speed and efficiency are reduced
Solution Approach 1:
The patent applies parameter changes by systematically varying material properties (work function, resistance, adhesion characteristics) across different regions of the conductive structure. The first material has low resistance for fast signal transmission, the second material has adhesion-promoting properties for grain growth, and the third material has high work function for efficient charge control. These parameter optimizations across multiple materials resolve the contradiction by achieving superior memory operation speed and efficiency while managing composition complexity through purposeful parameter selection for each material layer.
Data Source
AI summary
Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.


