NAND Memory Write Sequencing to Reduce Cell Disturbance
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Solution Overview
Problem
Current semiconductor storage devices face reliability issues due to disturbances during write operations, which can lead to incorrect data storage and reading failures, especially when multiple bits are written simultaneously.
Innovation Solution
A semiconductor storage device design that divides the write operation into two stages: a first write operation and a second write operation, where the first operation sets a coarse threshold voltage distribution, and the second operation refines it, minimizing the impact of disturbances from adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bits are written simultaneously to memory cells, then write speed is improved, but disturbance to adjacent memory cells increases causing reliability degradation
Solution Approach 1:
The patent segments the write operation into two distinct stages: a first write operation that writes to a first set of memory cells, and a second write operation that writes to a second set of memory cells. This segmentation prevents simultaneous writes to all memory cells, thereby reducing disturbance to adjacent cells while maintaining acceptable write speed through pipelined operation.
Solution Approach 2:
The patent performs the first write operation before the second write operation. By completing the first write to the first set of memory cells before initiating the second write to the second set, the system prepares the memory state in advance, reducing interference between simultaneous write operations and improving overall reliability.
2Productivity
If write operation is performed on all memory cells simultaneously, then productivity is improved, but disturbance to other string units increases causing threshold voltage shifts
Solution Approach 1:
The patent divides the memory cell array into a first set of memory cells and a second set of memory cells, and performs write operations on these sets sequentially rather than simultaneously. This segmentation isolates the disturbance effects to specific regions while maintaining overall system productivity through structured operation scheduling.
Solution Approach 2:
The patent applies different write operations to different sets of memory cells: the first write operation targets the first set while the second write operation targets the second set. This local differentiation allows the system to manage disturbance effects locally rather than globally, preventing widespread threshold voltage shifts across the entire memory array.
3Reliability
If first write operation is performed on all memory cells connected to a word line, then data writing completeness is improved, but disturbance to other string units connected to different word lines increases
Solution Approach 1:
The patent segments the write operation into a first write operation for a first set of memory cells and a second write operation for a second set of memory cells. This segmentation ensures that when writing to memory cells on one word line, other string units connected to different word lines are not simultaneously subjected to write disturbances, thereby maintaining data completeness while reducing harmful interference.
Solution Approach 2:
The patent extracts and isolates the write operation effects to specific sets of memory cells. By confining the first write operation to the first set and the second write operation to the second set, the system removes the harmful widespread disturbance that would occur with simultaneous writes across all string units, while still achieving complete data writing through the structured two-stage process.
Data Source
AI summary
A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.