NAND Write-Path Duty Cycle Correction for Timing Margin
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Solution Overview
Problem
High-speed data interfaces in electronic systems, such as NAND memory devices, face challenges with asynchronous clock timing margin loss due to channel and internal variations, leading to duty cycle distortion and reduced valid data eyes at flip flops, limiting operation bandwidth and margin.
Innovation Solution
Implementing duty cycle correction (DCC) technology on both data output and input paths, sharing calibration logic to improve timing margins and increase valid data windows, and using closed-loop DCC for write paths to compensate for duty cycle differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle correction is implemented on both read and write paths, then timing margins and valid data windows are improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration logic for read and write paths into a single shared resource. The calibration logic generates calibration patterns and determines duty cycle distortion compensation values, which are then applied by separate correction circuits in both read and write paths. This sharing of calibration functionality reduces overall device complexity while maintaining reliability improvements in both data paths.
Solution Approach 2:
The patent segments the duty cycle correction functionality into distinct components: a shared calibration logic unit and separate correction circuits for read and write paths. This segmentation allows the complex calibration function to be isolated and reused, reducing the overall complexity burden while providing targeted reliability improvements where needed.
2Productivity
If higher channel speeds are implemented, then productivity is improved, but duty cycle distortion increases leading to reduced timing margin
Solution Approach 1:
The patent implements feedback through calibration patterns that are passed through the data paths at high speeds. The calibration logic analyzes the returned patterns to determine duty cycle distortion characteristics, then applies compensation values to correct the distortion. This feedback mechanism enables the system to maintain timing margins even at higher channel speeds by dynamically adjusting for speed-related distortion.
Solution Approach 2:
The patent changes the parameter of duty cycle timing by applying compensation values derived from calibration. By measuring the actual duty cycle distortion at high speeds and adjusting the timing parameters through the correction circuits, the system maintains adequate timing margins while operating at higher productivity-enhancing speeds.
3Measurement precision
If separate calibration logic is implemented for read and write paths, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the calibration logic universal by designing it to serve both read and write paths. The same calibration pattern generation and analysis functionality is reused for calibrating both data directions, achieving adequate measurement precision for both paths without duplicating the calibration logic. This multi-functional approach reduces device complexity while maintaining sufficient calibration precision.
Data Source
AI summary
An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to provide duty cycle correction (DCC) for one or more write paths of the NAND memory. Other examples are disclosed and claimed.