NAND Flash Write-Command Segmentation for Bufferless Data Transfer
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Solution Overview
Problem
The existing NVMe data transmission protocols require data to be stored in a buffer before transmission through NAND channels, increasing the occupied area and cost of the master control chip.
Innovation Solution
A method and system for data transmission that divides write commands into sub-commands based on channel state and transmissible data size, assigning these sub-commands to idle flash memory channels for parallel writing, thereby reducing the need for buffer space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in a buffer before transmission through NAND channels, then data transmission reliability is improved, but the occupied area and cost of the master control chip increase
Solution Approach 1:
The patent extracts the buffer function from the master control chip by implementing a buffer-less architecture. Data is transmitted directly from the host interface through the NAND channels without requiring on-chip buffer storage, thereby reducing the occupied area of the master control chip while maintaining data transmission reliability through direct transmission pathways.
Solution Approach 2:
The patent introduces the host memory as an intermediary buffer for data storage before transmission. Instead of requiring a buffer within the master control chip, the system uses the host memory to hold data temporarily, allowing the controller to process and transmit data without dedicated buffer hardware, thus reducing chip area requirements.
2Stability of the object's composition
If data is stored in a buffer before transmission, then data transmission stability is improved, but the cost of the master control chip increases
Solution Approach 1:
The patent removes the buffer component from the master control chip design, extracting this function entirely from the controller. This elimination of hardware components directly reduces manufacturing complexity and cost while maintaining stable data transmission through the host memory intermediary and direct transmission pathways.
Solution Approach 2:
The patent leverages the host memory's universal buffering capability to serve multiple functions: data storage, temporary holding, and transmission coordination. This multi-functional use of existing host memory resources eliminates the need for dedicated buffer hardware in the controller, reducing both cost and complexity while maintaining transmission stability.
3Speed
If parallel access to multiple NAND channels is supported, then data transmission speed is improved, but the demand for buffer space increases
Solution Approach 1:
The patent segments the data transmission process into multiple parallel channels, dividing the data stream across multiple NAND channels simultaneously. This segmentation enables parallel access and increases transmission speed without requiring a single large buffer, as each channel processes data independently with smaller buffer requirements per channel.
Solution Approach 2:
The patent transitions from sequential single-channel transmission to parallel multi-channel transmission, adding a dimensional aspect to data flow. By utilizing multiple channels simultaneously, the system achieves higher throughput speeds while distributing buffer requirements across multiple smaller channels rather than requiring one large centralized buffer.
Data Source
AI summary
A method for data transmission, a controller, and a storage medium are provided. In response to receiving a write command to be processed, a data size and an address form corresponding to the write command are acquired; the write command is divided based on a transmissible data size corresponding to a flash memory channel for data transmission and a data size corresponding to the write command to obtain at least one sequentially executed sub-command, each of which has a corresponding sub-data size and corresponding sub-address information; a channel state of at least one flash memory channel is polled, and a sub-command is assigned to the flash memory channel when the channel state of the flash memory channel is idle; and a logical data block is acquired based on the sub-address information corresponding to the sub-command, and written into a NAND flash memory through the flash memory channel.