NAND Memory Write Control Using Threshold Voltage Classification
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in maintaining reliability due to the deterioration of memory cell transistors over time, which affects the threshold voltage distribution and data retention, leading to inefficiencies in write operations.
Innovation Solution
A semiconductor storage device with a controller that monitors and classifies memory cell transistors based on threshold voltage distribution width, adjusting the write operation parameters to optimize reliability by omitting or modifying verify operations based on the deterioration degree of the transistors, using artificial intelligence for more accurate classification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify operations are performed in write operations to ensure data reliability, then data retention is improved, but write operation time increases
Solution Approach 1:
The patent applies dynamics by making the write operation process adaptive rather than fixed. The controller dynamically adjusts the write operation parameters based on real-time monitoring of threshold voltage distribution width. When deterioration is detected, the system automatically modifies the number of verify operations or program pulses, transforming a static process into a flexible, condition-responsive operation that optimizes both reliability and time efficiency.
Solution Approach 2:
The patent implements feedback through continuous monitoring of threshold voltage distribution width during write operations. The controller receives feedback about the actual state of memory cell transistors and uses this information to adjust subsequent write operations. This closed-loop control ensures that verify operations are performed only when necessary, optimizing the balance between data retention and write operation time.
2Reliability
If standard write operations are performed on all memory cell transistors, then data retention is maintained, but write operation efficiency decreases due to unnecessary verify operations on healthy transistors
Solution Approach 1:
The patent applies local quality by treating different memory cell transistors differently based on their individual health status. Instead of applying uniform write operations to all transistors, the system monitors threshold voltage distribution width for each transistor and adjusts verify operations accordingly. Healthy transistors with narrow threshold voltage distributions receive simplified write operations, while deteriorated transistors receive enhanced verification, optimizing both reliability and efficiency at the local level.
Solution Approach 2:
The patent segments the memory cell transistor population into different groups based on their threshold voltage distribution characteristics. By monitoring and classifying transistors into categories (e.g., healthy vs. deteriorated), the system can apply differentiated write operation strategies to each segment. This segmentation allows the system to avoid unnecessary verify operations on healthy transistors while ensuring adequate verification for deteriorated ones.
3Reliability
If monitor and classify memory cell transistors based on threshold voltage distribution width, then write operation reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the memory system to monitor and classify its own components without external intervention. The controller automatically measures threshold voltage distribution width and performs classification based on predetermined criteria, making the system self-diagnostic and self-regulating. This autonomous operation reduces the need for complex external monitoring systems while maintaining high reliability.
Data Source
AI summary
A semiconductor storage device that is capable of improving reliability includes: a non-volatile memory provided with a block including a plurality of memory cell transistors connected to a word line; and a controller configured to monitor a threshold voltage distribution width of the plurality of memory cell transistors after performing at least one of an erasing operation on the block and a preliminary write operation on the plurality of memory cell transistors and to classify the plurality of memory cell transistors according to the threshold voltage distribution width of the plurality of memory cell transistors.