3D NAND Memory Write Voltage Control via Local Quality
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing the write operation of memory cell transistors, particularly in three-dimensional stacked NAND flash memory, due to variations in write characteristics across different memory cells, leading to inefficiencies and potential over-programming.
Innovation Solution
The semiconductor memory device employs a program loop mechanism with varying program voltages applied to the word line based on the write characteristics of individual memory cells, utilizing a first and second program mode to optimize the write operation and reduce the number of program loops required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed program voltage is applied to all memory cells during write operation, then the device complexity is reduced, but write reliability deteriorates due to variations in memory cell characteristics
Solution Approach 1:
The patent applies different program voltages to different memory cells based on their individual characteristics. The controller identifies memory cells with poor write characteristics and applies higher program voltages specifically to those cells, while using standard voltages for cells with good characteristics. This localized differentiation improves write reliability without requiring complex voltage control for the entire array.
Solution Approach 2:
The patent dynamically adjusts program voltages during the write operation based on real-time detection of memory cell characteristics. The controller monitors write results and adapts voltages accordingly, switching between first and second program modes. This dynamic adjustment allows the system to optimize write reliability without fixed, complex voltage scheduling.
2Reliability
If multiple program loops with varying voltages are applied to ensure reliable programming, then write reliability is improved, but write time increases
Solution Approach 1:
The controller performs preliminary detection of memory cell characteristics before the write operation. By pre-identifying cells with poor write characteristics, the system can prepare appropriate voltage sequences in advance and execute them efficiently during writing, avoiding unnecessary repeated loops for cells that don't require special attention.
Solution Approach 2:
The patent segments the memory array into different groups based on write characteristics: cells requiring first program mode (standard voltage) and cells requiring second program mode (higher voltage). This segmentation allows parallel processing with optimized voltages for each group, reducing overall write time while maintaining reliability.
3Speed
If high program voltages are applied to all memory cells, then programming speed is improved, but harmful effects increase due to over-programming
Solution Approach 1:
The patent applies high program voltages selectively only to memory cells that have been detected as having poor write characteristics. Cells with good characteristics receive standard voltages, preventing over-programming. This localized high-voltage application maintains programming speed for problematic cells without causing harmful effects in healthy cells.
Solution Approach 2:
The controller incorporates feedback mechanisms that monitor the results of write operations and adjust voltages accordingly. After initial programming attempts, the system detects whether cells were properly programmed and modifies subsequent voltage applications to avoid excessive voltages on cells that already have sufficient threshold voltages, thus preventing over-programming damage.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a first chip which includes first and second memory cells, a second chip which includes third and fourth memory cells, and a third chip which includes a row decoder. In a first program operation of the first memory cell, the row decoder applies a first program voltage to the first word line. In a first program operation of the second memory cell, the row decoder applies a second program voltage higher than the first program voltage to the first word line. In a first program operation of the third memory cell, the row decoder applies a third program voltage to the first word line. In a first program operation of the fourth memory cell, the row decoder applies a fourth program voltage higher than the third program voltage to the first word line.