Nano-Column Redistribution Lines for Delamination Resistance
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Solution Overview
Problem
Existing technologies face challenges in effectively distributing stress and preventing delamination in the formation of redistribution lines in semiconductor packages, particularly due to the random orientation of grain boundaries in polycrystalline structures, which can lead to structural integrity issues.
Innovation Solution
The formation of nano columns with stacked nano plates in redistribution lines, achieved through alternating high and low plating currents, ensures horizontal interfaces that distribute stress laterally and reduce delamination, while also confining copper atoms to prevent electro-migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline structures with random grain boundaries are used in redistribution lines, then manufacturing is simpler, but stress distribution is poor and delamination occurs
Solution Approach 1:
The polycrystalline structure is segmented into nanoscale columns with controlled grain boundaries. By dividing the material into finer segments (nano columns), the grain boundaries become more numerous but also more uniformly distributed, enabling better stress management while maintaining structural integrity.
Solution Approach 2:
The grain size parameter is changed from micrometer scale to nanometer scale. This parameter change transforms the random grain boundary structure into a controlled nano-columnar structure where grain boundaries are systematically arranged to provide stress distribution pathways, resolving the delamination issue while keeping the polycrystalline manufacturing advantage.
2Productivity
If conventional plating methods are used, then the process is simpler and faster, but copper atoms migrate due to electro-migration
Solution Approach 1:
The plating process uses periodic alternating current instead of direct current. This periodic action causes copper ions to oscillate during deposition, preventing unidirectional electro-migration while still achieving effective copper filling. The alternating current direction reverses periodically, counteracting the cumulative effect of electro-migration forces.
Solution Approach 2:
The plating current parameter is changed from direct current to alternating current with specific frequency and amplitude. This parameter change enables the plating process to maintain high productivity while simultaneously preventing electro-migration through the oscillatory deposition mechanism.
3Device complexity
If stress is concentrated in redistribution lines, then the structure is simpler, but delamination occurs reducing reliability
Solution Approach 1:
The stress distribution is segmented through the nano-columnar grain structure. The numerous nanoscale grain boundaries act as stress distribution pathways, breaking up concentrated stress into smaller distributed units. This segmentation approach maintains the overall structural simplicity while fundamentally improving stress distribution and delamination resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nano column structure enhances the structural integrity of redistribution lines by distributing stress horizontally, reducing delamination and preventing copper atom migration, thereby improving the reliability and performance of semiconductor packages.
Implementation Method 1
the plating comprises performing a plurality of plating cycles, with each of the plurality of plating cycles comprising: a first plating process performed using a first plating current density; and a second plating process performed using a second plating current density lower than the first plating current density
Data Source
AI summary
A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.


