Image Recognition Processor Error Detection Nano Core Array
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Solution Overview
Problem
In Advanced Driver Assistance Systems (ADAS) and autonomous driving, existing pattern recognition systems lack effective fault tolerance and error detection mechanisms, particularly in harsh environments, which can lead to significant accidents due to minor recognition errors.
Innovation Solution
An image recognition processor with a core array of nano cores arranged in rows and columns, an instruction memory, a feature memory, a kernel memory, and a difference checker that compares results to detect errors and apply fault tolerance within a predefined margin, ensuring reliable pattern recognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a distributed computing technique using a large number of CPU cores is used for pattern recognition, then processing speed and productivity are improved, but reliability deteriorates due to lack of fault tolerance and error detection mechanisms
Solution Approach 1:
The system segments the pattern recognition task across multiple nano cores arranged in rows and columns, where each core processes specific input data independently. This segmentation enables parallel processing for high productivity while allowing individual core failures to be isolated and detected without compromising the entire system's reliability.
Solution Approach 2:
The difference checker provides feedback by comparing results from multiple nano cores and detecting discrepancies. When recognition results differ between cores, the system triggers error detection and recovery mechanisms, ensuring reliability is maintained despite the distributed computing architecture's inherent vulnerability to individual core failures.
2Reliability
If fault tolerance mechanisms are added to pattern recognition systems, then reliability is improved, but device complexity increases
Solution Approach 1:
The difference checker merges results from multiple nano cores and compares them to detect errors. By combining the functional units of error detection, result comparison, and fault tolerance management into an integrated system, the patent reduces overall device complexity while maintaining high reliability through unified error handling mechanisms.
3Reliability
If error detection and recovery mechanisms are implemented, then reliability is improved, but processing time increases due to additional verification steps
Solution Approach 1:
The system performs preliminary error detection by having the difference checker compare results from multiple nano cores immediately after computation. This preliminary action detects errors early in the processing pipeline before further computations are performed, minimizing the time loss associated with error recovery while maintaining high reliability.
Data Source
AI summary
Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.